st_mult1.srr

veilog实现的状态机乘法器.可以参考

	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[7]
8) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[7]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[8]
9) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[8]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[9]
10) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[9]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[10]
11) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[10]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[11]
12) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[11]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[12]
13) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[12]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[13]
14) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[13]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[14]
15) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[14]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)