st_mult1.srr

veilog实现的状态机乘法器.可以参考

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Fri Mar 17 22:06:30 2006

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"D:\Program_Files\synplify81\fpga_81\lib\altera\altera.v"
@I::"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module st_mult1
@N:"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":1:7:1:14|Synthesizing module st_mult1

@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|Latch generated from always block for signal state_temp[1:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|Latch generated from always block for signal count[31:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|Latch generated from always block for signal bei_cheng_shu_Temp[31:0], probably caused by a missing assignment in an if or case stmt
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Mar 17 22:06:31 2006

###########################################################[
Version 8.1
Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May  6 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved


Warning: Found 34 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|Found combinational loop during mapping at net count[0]
1) instance work.st_mult1(verilog)-count[31:0], output net "count[0]" in work.st_mult1(verilog)
    input nets to instance:
	net "un9_count[0]" in work.st_mult1(verilog)
	net "un9_count[1]" in work.st_mult1(verilog)
	net "un9_count[2]" in work.st_mult1(verilog)
	net "un9_count[3]" in work.st_mult1(verilog)
	net "un9_count[4]" in work.st_mult1(verilog)
	net "un9_count[5]" in work.st_mult1(verilog)
	net "un9_count[6]" in work.st_mult1(verilog)
	net "un9_count[7]" in work.st_mult1(verilog)
	net "un9_count[8]" in work.st_mult1(verilog)
	net "un9_count[9]" in work.st_mult1(verilog)
	net "un9_count[10]" in work.st_mult1(verilog)
	net "un9_count[11]" in work.st_mult1(verilog)
	net "un9_count[12]" in work.st_mult1(verilog)
	net "un9_count[13]" in work.st_mult1(verilog)
	net "un9_count[14]" in work.st_mult1(verilog)
	net "un9_count[15]" in work.st_mult1(verilog)
	net "un9_count[16]" in work.st_mult1(verilog)
	net "un9_count[17]" in work.st_mult1(verilog)
	net "un9_count[18]" in work.st_mult1(verilog)
	net "un9_count[19]" in work.st_mult1(verilog)
	net "un9_count[20]" in work.st_mult1(verilog)
	net "un9_count[21]" in work.st_mult1(verilog)
	net "un9_count[22]" in work.st_mult1(verilog)
	net "un9_count[23]" in work.st_mult1(verilog)
	net "un9_count[24]" in work.st_mult1(verilog)
	net "un9_count[25]" in work.st_mult1(verilog)
	net "un9_count[26]" in work.st_mult1(verilog)
	net "un9_count[27]" in work.st_mult1(verilog)
	net "un9_count[28]" in work.st_mult1(verilog)
	net "un9_count[29]" in work.st_mult1(verilog)
	net "un9_count[30]" in work.st_mult1(verilog)
	net "un9_count[31]" in work.st_mult1(verilog)
	net "un1_current_state_2" in work.st_mult1(verilog)
	net "state_temp_0_sqmuxa" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[1]
2) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[1]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "count[4]" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[2]
3) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[2]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "count[4]" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[3]
4) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[3]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "count[4]" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|Found combinational loop during mapping at net count[4]
5) instance work.st_mult1(verilog)-count[31:0], output net "count[4]" in work.st_mult1(verilog)
    input nets to instance:
	net "un9_count[0]" in work.st_mult1(verilog)
	net "N_2" in work.st_mult1(verilog)
	net "N_3" in work.st_mult1(verilog)
	net "N_4" in work.st_mult1(verilog)
	net "un9_count[4]" in work.st_mult1(verilog)
	net "un9_count[5]" in work.st_mult1(verilog)
	net "un9_count[6]" in work.st_mult1(verilog)
	net "un9_count[7]" in work.st_mult1(verilog)
	net "un9_count[8]" in work.st_mult1(verilog)
	net "un9_count[9]" in work.st_mult1(verilog)
	net "un9_count[10]" in work.st_mult1(verilog)
	net "un9_count[11]" in work.st_mult1(verilog)
	net "un9_count[12]" in work.st_mult1(verilog)
	net "un9_count[13]" in work.st_mult1(verilog)
	net "un9_count[14]" in work.st_mult1(verilog)
	net "un9_count[15]" in work.st_mult1(verilog)
	net "un9_count[16]" in work.st_mult1(verilog)
	net "un9_count[17]" in work.st_mult1(verilog)
	net "un9_count[18]" in work.st_mult1(verilog)
	net "un9_count[19]" in work.st_mult1(verilog)
	net "un9_count[20]" in work.st_mult1(verilog)
	net "un9_count[21]" in work.st_mult1(verilog)
	net "un9_count[22]" in work.st_mult1(verilog)
	net "un9_count[23]" in work.st_mult1(verilog)
	net "un9_count[24]" in work.st_mult1(verilog)
	net "un9_count[25]" in work.st_mult1(verilog)
	net "un9_count[26]" in work.st_mult1(verilog)
	net "un9_count[27]" in work.st_mult1(verilog)
	net "un9_count[28]" in work.st_mult1(verilog)
	net "un9_count[29]" in work.st_mult1(verilog)
	net "un9_count[30]" in work.st_mult1(verilog)
	net "un9_count[31]" in work.st_mult1(verilog)
	net "un1_current_state_2" in work.st_mult1(verilog)
	net "state_temp_0_sqmuxa" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[5]
6) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[5]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|Found combinational loop during mapping at net un9_count[6]
7) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[6]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)