st_mult1.plg

来自「veilog实现的状态机乘法器.可以参考」· PLG 代码 · 共 19 行

@P:  Part : EPF10K10TC144-3
@P:  Worst Slack : 978.078
@P:  st_mult1|clk - Estimated Frequency : 45.6 MHz
@P:  st_mult1|clk - Requested Frequency : 1.0 MHz
@P:  st_mult1|clk - Estimated Period : 21.922
@P:  st_mult1|clk - Requested Period : 1000.000
@P:  st_mult1|clk - Slack : 978.078
@P:  System - Estimated Frequency : 67.3 MHz
@P:  System - Requested Frequency : 1.0 MHz
@P:  System - Estimated Period : 14.868
@P:  System - Requested Period : 1000.000
@P:  System - Slack : 985.132
@P: st_mult1 Part : epf10k10tc144-3
@P: st_mult1 Total LUTs: : 117 of 576 (20%) 
@P: st_mult1 Logic resources : 117 LCs of 576 (20%) 
@P: st_mult1 Register bits : 2
@P: st_mult1 EABs : 0
@P: st_mult1 I/O cells : 67