st_mult1.msg

veilog实现的状态机乘法器.可以参考

@TM:1142601804
@W: BN137 :"":0:0:0:-1|Found combinational loop during mapping at net N_429_i
@W: BN137 :"":0:0:0:-1|Found combinational loop during mapping at net N_429_i
@W: BN137 :"":0:0:0:-1|Found combinational loop during mapping at net N_429_i
@TM:1142512732
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1142512720
@N:  :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":1:7:1:14|Synthesizing module st_mult1
@TM:1142601804
@W:  :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|M
@TM:1142601798
@W: BN134 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|M
@TM:1142601804
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|M
@TM:1142601798
@W: CL118 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":26:1:26:4|M
@TM:1142602470
@W:  :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":49:1:49:5|M
@TM:1142602466
@W: BN134 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|M
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":52:12:52:19|M