st_mult1_srr.htm

veilog实现的状态机乘法器.可以参考

	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:52:12:52:20:@W:BN137:@XP_MSG">st_mult1.v(52)</a><!@TM:1142604400> | Found combinational loop during mapping at net un9_count[21]</font>
22) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[21]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:52:12:52:20:@W:BN137:@XP_MSG">st_mult1.v(52)</a><!@TM:1142604400> | Found combinational loop during mapping at net un9_count[22]</font>
23) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[22]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:52:12:52:20:@W:BN137:@XP_MSG">st_mult1.v(52)</a><!@TM:1142604400> | Found combinational loop during mapping at net un9_count[23]</font>
24) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[23]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:52:12:52:20:@W:BN137:@XP_MSG">st_mult1.v(52)</a><!@TM:1142604400> | Found combinational loop during mapping at net un9_count[24]</font>
25) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[24]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:52:12:52:20:@W:BN137:@XP_MSG">st_mult1.v(52)</a><!@TM:1142604400> | Found combinational loop during mapping at net un9_count[25]</font>
26) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[25]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:52:12:52:20:@W:BN137:@XP_MSG">st_mult1.v(52)</a><!@TM:1142604400> | Found combinational loop during mapping at net un9_count[26]</font>
27) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[26]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)
	net "count[6]" in work.st_mult1(verilog)
	net "count[7]" in work.st_mult1(verilog)
	net "count[8]" in work.st_mult1(verilog)
	net "count[9]" in work.st_mult1(verilog)
	net "count[10]" in work.st_mult1(verilog)
	net "count[11]" in work.st_mult1(verilog)
	net "count[12]" in work.st_mult1(verilog)
	net "count[13]" in work.st_mult1(verilog)
	net "count[14]" in work.st_mult1(verilog)
	net "count[15]" in work.st_mult1(verilog)
	net "count[16]" in work.st_mult1(verilog)
	net "count[17]" in work.st_mult1(verilog)
	net "count[18]" in work.st_mult1(verilog)
	net "count[19]" in work.st_mult1(verilog)
	net "count[20]" in work.st_mult1(verilog)
	net "count[21]" in work.st_mult1(verilog)
	net "count[22]" in work.st_mult1(verilog)
	net "count[23]" in work.st_mult1(verilog)
	net "count[24]" in work.st_mult1(verilog)
	net "count[25]" in work.st_mult1(verilog)
	net "count[26]" in work.st_mult1(verilog)
	net "count[27]" in work.st_mult1(verilog)
	net "count[28]" in work.st_mult1(verilog)
	net "count[29]" in work.st_mult1(verilog)
	net "count[30]" in work.st_mult1(verilog)
	net "count[31]" in work.st_mult1(verilog)
	net "VCC" in work.st_mult1(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:52:12:52:20:@W:BN137:@XP_MSG">st_mult1.v(52)</a><!@TM:1142604400> | Found combinational loop during mapping at net un9_count[27]</font>
28) instance work.st_mult1(verilog)-un9_count[31:0], output net "un9_count[27]" in work.st_mult1(verilog)
    input nets to instance:
	net "N_1" in work.st_mult1(verilog)
	net "count[1]" in work.st_mult1(verilog)
	net "count[2]" in work.st_mult1(verilog)
	net "count[3]" in work.st_mult1(verilog)
	net "N_5" in work.st_mult1(verilog)
	net "count[5]" in work.st_mult1(verilog)