📄 st_mult1.rpt
字号:
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
96 - - A -- OUTPUT 0 1 0 0 ok
17 - - B -- OUTPUT 0 1 0 0 result0
91 - - B -- OUTPUT 0 1 0 0 result1
90 - - B -- OUTPUT 0 1 0 0 result2
37 - - - 23 OUTPUT 0 1 0 0 result3
142 - - - 23 OUTPUT 0 1 0 0 result4
8 - - A -- OUTPUT 0 1 0 0 result5
140 - - - 21 OUTPUT 0 1 0 0 result6
133 - - - 17 OUTPUT 0 1 0 0 result7
144 - - - 24 OUTPUT 0 1 0 0 result8
11 - - A -- OUTPUT 0 1 0 0 result9
128 - - - 13 OUTPUT 0 1 0 0 result10
130 - - - 14 OUTPUT 0 1 0 0 result11
44 - - - 18 OUTPUT 0 1 0 0 result12
89 - - B -- OUTPUT 0 1 0 0 result13
19 - - B -- OUTPUT 0 1 0 0 result14
141 - - - 22 OUTPUT 0 1 0 0 result15
33 - - C -- OUTPUT 0 1 0 0 result16
22 - - B -- OUTPUT 0 1 0 0 result17
143 - - - 24 OUTPUT 0 1 0 0 result18
49 - - - 14 OUTPUT 0 1 0 0 result19
21 - - B -- OUTPUT 0 1 0 0 result20
23 - - B -- OUTPUT 0 1 0 0 result21
51 - - - 13 OUTPUT 0 1 0 0 result22
43 - - - 18 OUTPUT 0 1 0 0 result23
88 - - B -- OUTPUT 0 1 0 0 result24
32 - - C -- OUTPUT 0 1 0 0 result25
20 - - B -- OUTPUT 0 1 0 0 result26
36 - - - 24 OUTPUT 0 1 0 0 result27
86 - - B -- OUTPUT 0 1 0 0 result28
87 - - B -- OUTPUT 0 1 0 0 result29
39 - - - 21 OUTPUT 0 1 0 0 result30
38 - - - 22 OUTPUT 0 1 0 0 result31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_3\maxplus\st_mult1.rpt
st_mult1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 11 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_1_~7
- 4 - B 11 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_2_~7
- 7 - B 11 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_3_~7
- 2 - B 14 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_4_~7
- 3 - B 14 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_5_~7
- 7 - B 14 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_6_~7
- 8 - B 14 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_7_~7
- 1 - B 15 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_8_~7
- 3 - B 15 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_9_~7
- 4 - B 15 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_10_~7
- 7 - B 15 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_11_~7
- 3 - B 06 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_12_~7
- 5 - B 06 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_13_~7
- 6 - B 06 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_14_~7
- 8 - B 06 OR2 1 3 0 1 bei_cheng_shu_Temp_1_i_m2_15_~7
- 5 - A 06 AND2 0 2 0 51 bei_cheng_shu_Temp_1_i_o2_16_~1
- 8 - A 09 OR2 0 4 0 1 count_1_i_2_~10
- 5 - A 07 OR2 0 4 0 1 count_1_i_4_~10
- 8 - A 07 OR2 ! 0 4 0 1 current_state_ns_0_0_a2_1_~7
- 7 - A 07 OR2 ! 0 4 0 1 current_state_ns_0_0_a2_2_1_~3
- 2 - B 11 DFFE + 1 1 0 55 current_state_0_ (current_state0)
- 3 - A 07 DFFE + 1 2 0 40 current_state_1_ (current_state1)
- 8 - B 11 LCELL 1 2 0 2 |lpm_latch:bei_cheng_shu_Temp_0_|latches0
- 6 - B 11 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_1_|latches0
- 5 - B 11 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_2_|latches0
- 3 - B 11 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_3_|latches0
- 6 - B 14 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_4_|latches0
- 1 - B 14 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_5_|latches0
- 4 - B 14 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_6_|latches0
- 5 - B 14 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_7_|latches0
- 2 - B 15 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_8_|latches0
- 8 - B 15 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_9_|latches0
- 5 - B 15 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_10_|latches0
- 6 - B 15 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_11_|latches0
- 4 - B 06 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_12_|latches0
- 2 - B 06 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_13_|latches0
- 7 - B 06 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_14_|latches0
- 1 - B 06 LCELL 0 2 0 2 |lpm_latch:bei_cheng_shu_Temp_15_|latches0
- 6 - B 16 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_16_|latches0
- 1 - B 16 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_17_|latches0
- 4 - B 16 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_18_|latches0
- 2 - B 16 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_19_|latches0
- 3 - B 16 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_20_|latches0
- 5 - B 16 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_21_|latches0
- 7 - B 16 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_22_|latches0
- 8 - B 16 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_23_|latches0
- 6 - B 19 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_24_|latches0
- 1 - B 19 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_25_|latches0
- 4 - B 19 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_26_|latches0
- 5 - B 19 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_27_|latches0
- 7 - B 19 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_28_|latches0
- 3 - B 19 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_29_|latches0
- 2 - B 19 LCELL 0 3 0 2 |lpm_latch:bei_cheng_shu_Temp_30_|latches0
- 8 - B 19 LCELL 0 3 0 1 |lpm_latch:bei_cheng_shu_Temp_31_|latches0
- 1 - A 06 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_0_|latches0
- 3 - A 09 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_1_|latches0
- 3 - A 05 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_2_|latches0
- 5 - A 01 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_3_|latches0
- 7 - A 06 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_4_|latches0
- 5 - A 09 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_5_|latches0
- 5 - A 05 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_6_|latches0
- 7 - A 01 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_7_|latches0
- 4 - A 06 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_8_|latches0
- 4 - A 09 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_9_|latches0
- 4 - A 05 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_10_|latches0
- 6 - A 01 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_11_|latches0
- 8 - A 06 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_12_|latches0
- 7 - A 09 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_13_|latches0
- 6 - A 05 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_14_|latches0
- 8 - A 01 LCELL 1 1 0 1 |lpm_latch:cheng_shu_temp_15_|latches0
- 1 - A 12 LCELL 0 2 0 6 |lpm_latch:count_0_|latches0
- 1 - A 07 LCELL 0 3 0 5 |lpm_latch:count_1_|latches0
- 6 - A 09 LCELL 0 2 0 11 |lpm_latch:count_2_|latches0
- 2 - A 07 LCELL 0 3 0 10 |lpm_latch:count_3_|latches0
- 6 - A 07 LCELL 0 2 0 2 |lpm_latch:count_4_|latches0
- 6 - A 06 OR2 0 3 1 0 |lpm_latch:ok1|:49
- 1 - B 17 OR2 0 3 1 1 |lpm_latch:result_0_|:49
- 2 - B 21 OR2 0 3 1 1 |lpm_latch:result_1_|:49
- 4 - B 23 OR2 0 3 1 1 |lpm_latch:result_2_|:49
- 8 - B 23 OR2 0 3 1 1 |lpm_latch:result_3_|:49
- 7 - B 23 OR2 0 3 1 1 |lpm_latch:result_4_|:49
- 2 - B 17 OR2 0 3 1 1 |lpm_latch:result_5_|:49
- 8 - B 21 OR2 0 3 1 1 |lpm_latch:result_6_|:49
- 6 - B 17 OR2 0 3 1 1 |lpm_latch:result_7_|:49
- 2 - B 23 OR2 0 3 1 1 |lpm_latch:result_8_|:49
- 5 - B 23 OR2 0 3 1 1 |lpm_latch:result_9_|:49
- 5 - B 13 OR2 0 3 1 1 |lpm_latch:result_10_|:49
- 2 - B 13 OR2 0 3 1 1 |lpm_latch:result_11_|:49
- 4 - B 17 OR2 0 3 1 1 |lpm_latch:result_12_|:49
- 5 - B 21 OR2 0 3 1 1 |lpm_latch:result_13_|:49
- 3 - B 13 OR2 0 3 1 1 |lpm_latch:result_14_|:49
- 3 - B 21 OR2 0 3 1 1 |lpm_latch:result_15_|:49
- 8 - B 13 OR2 0 3 1 1 |lpm_latch:result_16_|:49
- 6 - B 23 OR2 0 3 1 1 |lpm_latch:result_17_|:49
- 3 - B 23 OR2 0 3 1 1 |lpm_latch:result_18_|:49
- 1 - B 13 OR2 0 3 1 1 |lpm_latch:result_19_|:49
- 5 - B 17 OR2 0 3 1 1 |lpm_latch:result_20_|:49
- 7 - B 21 OR2 0 3 1 1 |lpm_latch:result_21_|:49
- 4 - B 13 OR2 0 3 1 1 |lpm_latch:result_22_|:49
- 3 - B 17 OR2 0 3 1 1 |lpm_latch:result_23_|:49
- 6 - B 13 OR2 0 3 1 1 |lpm_latch:result_24_|:49
- 7 - B 13 OR2 0 3 1 1 |lpm_latch:result_25_|:49
- 4 - B 21 OR2 0 3 1 1 |lpm_latch:result_26_|:49
- 1 - B 23 OR2 0 3 1 1 |lpm_latch:result_27_|:49
- 8 - B 17 OR2 0 3 1 1 |lpm_latch:result_28_|:49
- 7 - B 17 OR2 0 3 1 1 |lpm_latch:result_29_|:49
- 6 - B 21 OR2 0 3 1 1 |lpm_latch:result_30_|:49
- 1 - B 21 OR2 0 3 1 1 |lpm_latch:result_31_|:49
- 1 - B 01 AND2 0 2 0 32 un1_cheng_shu_temp_1_0_a2~1
- 2 - A 06 CASCADE 0 4 0 1 N_9 (un1_cheng_shu_temp_3_0_cas)
- 1 - A 05 CASCADE 0 4 0 1 N_5 (un1_cheng_shu_temp_6_0_cas)
- 1 - A 09 CASCADE 0 4 0 1 N_7 (un1_cheng_shu_temp_10_0_cas)
- 1 - A 01 CASCADE 0 4 0 1 N_3 (un1_cheng_shu_temp_13_0_cas)
- 3 - A 01 CASCADE 0 4 0 1 N_1 (un1_cheng_shu_temp_15_cas1)
- 4 - A 07 OR2 ! 0 3 0 3 un4_count_anc2~2
- 1 - B 18 LCELL 0 2 0 1 un4_result_add0_lx_0 (un4_result_add0_clc)
- 2 - B 18 LCELL 0 2 0 1 un4_result_add1_lx_0 (un4_result_add1_clc)
- 3 - B 18 LCELL 0 2 0 1 un4_result_add2_lx_0 (un4_result_add2_clc)
- 4 - B 18 LCELL 0 2 0 1 un4_result_add3_lx_0 (un4_result_add3_clc)
- 5 - B 18 LCELL 0 2 0 1 un4_result_add4_lx_0 (un4_result_add4_clc)
- 6 - B 18 LCELL 0 2 0 1 un4_result_add5_lx_0 (un4_result_add5_clc)
- 7 - B 18 LCELL 0 2 0 1 un4_result_add6_lx_0 (un4_result_add6_clc)
- 8 - B 18 LCELL 0 2 0 1 un4_result_add7_lx_0 (un4_result_add7_clc)
- 1 - B 20 LCELL 0 2 0 1 un4_result_add8_lx_0 (un4_result_add8_clc)
- 2 - B 20 LCELL 0 2 0 1 un4_result_add9_lx_0 (un4_result_add9_clc)
- 3 - B 20 LCELL 0 2 0 1 un4_result_add10_lx_0 (un4_result_add10_clc)
- 4 - B 20 LCELL 0 2 0 1 un4_result_add11_lx_0 (un4_result_add11_clc)
- 5 - B 20 LCELL 0 2 0 1 un4_result_add12_lx_0 (un4_result_add12_clc)
- 6 - B 20 LCELL 0 2 0 1 un4_result_add13_lx_0 (un4_result_add13_clc)
- 7 - B 20 LCELL 0 2 0 1 un4_result_add14_lx_0 (un4_result_add14_clc)
- 8 - B 20 LCELL 0 2 0 1 un4_result_add15_lx_0 (un4_result_add15_clc)
- 1 - B 22 LCELL 0 2 0 1 un4_result_add16_lx_0 (un4_result_add16_clc)
- 2 - B 22 LCELL 0 2 0 1 un4_result_add17_lx_0 (un4_result_add17_clc)
- 3 - B 22 LCELL 0 2 0 1 un4_result_add18_lx_0 (un4_result_add18_clc)
- 4 - B 22 LCELL 0 2 0 1 un4_result_add19_lx_0 (un4_result_add19_clc)
- 5 - B 22 LCELL 0 2 0 1 un4_result_add20_lx_0 (un4_result_add20_clc)
- 6 - B 22 LCELL 0 2 0 1 un4_result_add21_lx_0 (un4_result_add21_clc)
- 7 - B 22 LCELL 0 2 0 1 un4_result_add22_lx_0 (un4_result_add22_clc)
- 8 - B 22 LCELL 0 2 0 1 un4_result_add23_lx_0 (un4_result_add23_clc)
- 1 - B 24 LCELL 0 2 0 1 un4_result_add24_lx_0 (un4_result_add24_clc)
- 2 - B 24 LCELL 0 2 0 1 un4_result_add25_lx_0 (un4_result_add25_clc)
- 3 - B 24 LCELL 0 2 0 1 un4_result_add26_lx_0 (un4_result_add26_clc)
- 4 - B 24 LCELL 0 2 0 1 un4_result_add27_lx_0 (un4_result_add27_clc)
- 5 - B 24 LCELL 0 2 0 1 un4_result_add28_lx_0 (un4_result_add28_clc)
- 6 - B 24 LCELL 0 2 0 1 un4_result_add29_lx_0 (un4_result_add29_clc)
- 7 - B 24 LCELL 0 2 0 1 un4_result_add30_lx_0 (un4_result_add30_clc)
- 8 - B 24 LCELL 0 2 0 1 un4_result_add31 (:218)
- 4 - A 01 LCELL 0 5 0 1 un1_cheng_shu_temp_15_0_i_m2 (:222)
- 2 - A 01 LCELL 0 5 0 1 un1_cheng_shu_temp_13_0 (:225)
- 2 - A 05 LCELL 0 5 0 1 un1_cheng_shu_temp_6_0 (:228)
- 2 - A 09 LCELL 0 5 0 1 un1_cheng_shu_temp_10_0 (:231)
- 3 - A 06 LCELL 0 5 0 1 un1_cheng_shu_temp_3_0 (:234)
- 1 - B 18 CARRY 0 2 0 1 |carry_sum:un4_result_add0_cry|:31
- 2 - B 18 CARRY 0 3 0 1 |carry_sum:un4_result_add1_cry|:31
- 3 - B 18 CARRY 0 3 0 1 |carry_sum:un4_result_add2_cry|:31
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