📄 st_mult1.rpt
字号:
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
cheng_shu7 | 7 102 | RESERVED
result5 | 8 101 | cheng_shu13
cheng_shu9 | 9 100 | cheng_shu4
cheng_shu12 | 10 99 | cheng_shu5
result9 | 11 98 | cheng_shu11
cheng_shu6 | 12 97 | cheng_shu14
cheng_shu15 | 13 96 | ok
cheng_shu3 | 14 95 | cheng_shu1
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
result0 | 17 92 | bei_cheng_shu9
bei_cheng_shu7 | 18 91 | result1
result14 | 19 EPF10K10TC144-3 90 | result2
result26 | 20 89 | result13
result20 | 21 88 | result24
result17 | 22 87 | result29
result21 | 23 86 | result28
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | RESERVED
RESERVED | 27 82 | RESERVED
RESERVED | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
result25 | 32 77 | ^MSEL0
result16 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
result27 | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
r r r G R b r r V R R R r G r V V r C c G G R b V R R b b G R R R R V R
e e e N E e e e C E E E e N e C C s L h N N E e C E E e e N E E E E C E
s s s D S i s s C S S S s D s C C t K e D D S i C S S i i D S S S S C S
u u u I E _ u u I E E E u I u I I n I I E _ I E E _ _ I E E E E I E
l l l O R c l l O R R R l O l N N g N N R c O R R c c O R R R R O R
t t t V h t t V V V t t T T _ T T V h V V h h V V V V V
3 3 3 E e 2 1 E E E 1 2 s E e E E e e E E E E E
1 0 D n 3 2 D D D 9 2 h D n D D n n D D D D D
g u g g g
_ 0 _ _ _
s s s s
h h h h
u u u u
6 1 3 0
4
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_3\maxplus\st_mult1.rpt
st_mult1
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 12/22( 54%)
A5 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
A6 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
A7 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
A9 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
A12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B6 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
B11 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
B13 8/ 8(100%) 6/ 8( 75%) 8/ 8(100%) 0/2 0/2 10/22( 45%)
B14 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
B15 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
B16 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 3/22( 13%)
B17 8/ 8(100%) 4/ 8( 50%) 8/ 8(100%) 0/2 0/2 10/22( 45%)
B18 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 16/22( 72%)
B19 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 0/2 0/2 3/22( 13%)
B20 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 16/22( 72%)
B21 8/ 8(100%) 4/ 8( 50%) 8/ 8(100%) 0/2 0/2 10/22( 45%)
B22 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 16/22( 72%)
B23 8/ 8(100%) 6/ 8( 75%) 8/ 8(100%) 0/2 0/2 10/22( 45%)
B24 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 16/22( 72%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 61/96 ( 63%)
Total logic cells used: 152/576 ( 26%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.30/4 ( 82%)
Total fan-in: 503/2304 ( 21%)
Total input pins required: 34
Total input I/O cell registers required: 0
Total output pins required: 33
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 152
Total flipflops required: 2
Total packed registers required: 0
Total logic cells in carry chains: 32
Total number of carry chains: 1
Total number of carry chains of length 1-8 : 0
Total number of carry chains of length 9-16: 0
Total number of carry chains of length 17-24: 0
Total number of carry chains of length 25-32: 1
Total logic cells in cascade chains: 10
Total number of cascade chains: 5
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 0 0 0 6 8 8 0 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 39/0
B: 1 0 0 0 0 8 0 0 0 0 8 0 0 8 8 8 8 8 8 8 8 8 8 8 8 113/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 9 0 0 0 6 16 8 0 8 0 8 1 0 8 8 8 8 8 8 8 8 8 8 8 8 152/0
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_3\maxplus\st_mult1.rpt
st_mult1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
65 - - - 09 INPUT 0 0 0 1 bei_cheng_shu0
117 - - - 06 INPUT 0 0 0 1 bei_cheng_shu1
110 - - - 01 INPUT 0 0 0 1 bei_cheng_shu2
64 - - - 10 INPUT 0 0 0 1 bei_cheng_shu3
132 - - - 16 INPUT 0 0 0 1 bei_cheng_shu4
137 - - - 19 INPUT 0 0 0 1 bei_cheng_shu5
42 - - - 19 INPUT 0 0 0 1 bei_cheng_shu6
18 - - B -- INPUT 0 0 0 1 bei_cheng_shu7
138 - - - 20 INPUT 0 0 0 1 bei_cheng_shu8
92 - - B -- INPUT 0 0 0 1 bei_cheng_shu9
135 - - - 18 INPUT 0 0 0 1 bei_cheng_shu10
131 - - - 15 INPUT 0 0 0 1 bei_cheng_shu11
111 - - - 02 INPUT 0 0 0 1 bei_cheng_shu12
120 - - - 09 INPUT 0 0 0 1 bei_cheng_shu13
60 - - - 12 INPUT 0 0 0 1 bei_cheng_shu14
116 - - - 05 INPUT 0 0 0 1 bei_cheng_shu15
56 - - - -- INPUT 0 0 0 1 cheng_shu0
95 - - A -- INPUT 0 0 0 1 cheng_shu1
126 - - - -- INPUT 0 0 0 1 cheng_shu2
14 - - A -- INPUT 0 0 0 1 cheng_shu3
100 - - A -- INPUT 0 0 0 1 cheng_shu4
99 - - A -- INPUT 0 0 0 1 cheng_shu5
12 - - A -- INPUT 0 0 0 1 cheng_shu6
7 - - A -- INPUT 0 0 0 1 cheng_shu7
124 - - - -- INPUT 0 0 0 1 cheng_shu8
9 - - A -- INPUT 0 0 0 1 cheng_shu9
125 - - - -- INPUT 0 0 0 1 cheng_shu10
98 - - A -- INPUT 0 0 0 1 cheng_shu11
10 - - A -- INPUT 0 0 0 1 cheng_shu12
101 - - A -- INPUT 0 0 0 1 cheng_shu13
97 - - A -- INPUT 0 0 0 1 cheng_shu14
13 - - A -- INPUT 0 0 0 1 cheng_shu15
55 - - - -- INPUT G 0 0 0 0 CLK
54 - - - -- INPUT 0 0 0 2 rst
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:g:\taoyuhui\synplifywork_new\statemachine_mult\rev_3\maxplus\st_mult1.rpt
st_mult1
** OUTPUTS **
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