st_mult1.sat

veilog实现的状态机乘法器.可以参考

# Run with quartus_sh -t <x_cons.tcl>
define_design_name {st_mult1}
define_synthesis -family FLEX10K
define_synthesis -device {EPF10K10TC144-3}
define_synthesis -style WYSIWYG
define_synthesis -inverter_push_back OFF
clear_auto_cliques
define_clock {} -freq 1.0
define_clock {|clk} -period 1000.000
define_output_delay {|ok} 0.1 -clock {|clk}
define_output_delay {|result0} 0.1
define_output_delay {|result1} 0.1
define_output_delay {|result2} 0.1
define_output_delay {|result3} 0.1
define_output_delay {|result4} 0.1
define_output_delay {|result5} 0.1
define_output_delay {|result6} 0.1
define_output_delay {|result7} 0.1
define_output_delay {|result8} 0.1
define_output_delay {|result9} 0.1
define_output_delay {|result10} 0.1
define_output_delay {|result11} 0.1
define_output_delay {|result12} 0.1
define_output_delay {|result13} 0.1
define_output_delay {|result14} 0.1
define_output_delay {|result15} 0.1
define_output_delay {|result16} 0.1
define_output_delay {|result17} 0.1
define_output_delay {|result18} 0.1
define_output_delay {|result19} 0.1
define_output_delay {|result20} 0.1
define_output_delay {|result21} 0.1
define_output_delay {|result22} 0.1
define_output_delay {|result23} 0.1
define_output_delay {|result24} 0.1
define_output_delay {|result25} 0.1
define_output_delay {|result26} 0.1
define_output_delay {|result27} 0.1
define_output_delay {|result28} 0.1
define_output_delay {|result29} 0.1
define_output_delay {|result30} 0.1
define_output_delay {|result31} 0.1
define_input_delay {|cheng_shu0} 0.1
define_input_delay {|cheng_shu1} 0.1
define_input_delay {|cheng_shu2} 0.1
define_input_delay {|cheng_shu3} 0.1
define_input_delay {|cheng_shu4} 0.1
define_input_delay {|cheng_shu5} 0.1
define_input_delay {|cheng_shu6} 0.1
define_input_delay {|cheng_shu7} 0.1
define_input_delay {|cheng_shu8} 0.1
define_input_delay {|cheng_shu9} 0.1
define_input_delay {|cheng_shu10} 0.1
define_input_delay {|cheng_shu11} 0.1
define_input_delay {|cheng_shu12} 0.1
define_input_delay {|cheng_shu13} 0.1
define_input_delay {|cheng_shu14} 0.1
define_input_delay {|cheng_shu15} 0.1
define_input_delay {|bei_cheng_shu0} 0.1
define_input_delay {|bei_cheng_shu1} 0.1
define_input_delay {|bei_cheng_shu2} 0.1
define_input_delay {|bei_cheng_shu3} 0.1
define_input_delay {|bei_cheng_shu4} 0.1
define_input_delay {|bei_cheng_shu5} 0.1
define_input_delay {|bei_cheng_shu6} 0.1
define_input_delay {|bei_cheng_shu7} 0.1
define_input_delay {|bei_cheng_shu8} 0.1
define_input_delay {|bei_cheng_shu9} 0.1
define_input_delay {|bei_cheng_shu10} 0.1
define_input_delay {|bei_cheng_shu11} 0.1
define_input_delay {|bei_cheng_shu12} 0.1
define_input_delay {|bei_cheng_shu13} 0.1
define_input_delay {|bei_cheng_shu14} 0.1
define_input_delay {|bei_cheng_shu15} 0.1
define_input_delay {|clk} 0.1
define_input_delay {|rst} 0.1

log_puts {All Constraints processed!}