st_mult1.srs

veilog实现的状态机乘法器.可以参考

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Sat Mar 18 10:37:11 2006
#
#
#OPTIONS:"|-fixsmult|-nram|-divnmod|-I|G:\\taoyuhui\\synplifywork_new\\statemachine_mult\\|-I|D:\\Program_Files\\synplify81\\fpga_81\\lib|-v2001|-devicelib|D:\\Program_Files\\synplify81\\fpga_81\\lib\\altera\\altera.v|-autosm|-fid2|-sharing|off|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"D:\\Program_Files\\synplify81\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"D:\\Program_Files\\synplify81\\fpga_81\\lib\\altera\\altera.v":1046175234
#CUR:"D:\\Program_Files\\synplify81\\fpga_81\\lib\\altera\\altera.v":1046175234
#CUR:"G:\\taoyuhui\\synplifywork_new\\statemachine_mult\\st_mult1.v":1142649428
#CUR:"G:\\taoyuhui\\synplifywork_new\\statemachine_mult\\st_mult1.v":1142649428
f "D:\Program_Files\synplify81\fpga_81\lib\altera\altera.v"; # file 0
af .is_verilog 1;
f "G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v"; # file 1
af .is_verilog 1;
@E
@ 
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