st_mult1.srr

veilog实现的状态机乘法器.可以参考

	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)
	net "un4_result[15]" in work.st_mult1(verilog)
	net "un4_result[16]" in work.st_mult1(verilog)
	net "un4_result[17]" in work.st_mult1(verilog)
	net "un4_result[18]" in work.st_mult1(verilog)
	net "un4_result[19]" in work.st_mult1(verilog)
	net "un4_result[20]" in work.st_mult1(verilog)
	net "un4_result[21]" in work.st_mult1(verilog)
	net "un4_result[22]" in work.st_mult1(verilog)
	net "un4_result[23]" in work.st_mult1(verilog)
	net "un4_result[24]" in work.st_mult1(verilog)
	net "un4_result[25]" in work.st_mult1(verilog)
	net "un4_result[26]" in work.st_mult1(verilog)
	net "un4_result[27]" in work.st_mult1(verilog)
	net "un4_result[28]" in work.st_mult1(verilog)
	net "un4_result[29]" in work.st_mult1(verilog)
	net "un4_result[30]" in work.st_mult1(verilog)
	net "un4_result[31]" in work.st_mult1(verilog)
	net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
	net "current_state[0]" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Found combinational loop during mapping at net result[13]
14) instance work.st_mult1(verilog)-result[31:0], output net "result[13]" in work.st_mult1(verilog)
    input nets to instance:
	net "un4_result[0]" in work.st_mult1(verilog)
	net "un4_result[1]" in work.st_mult1(verilog)
	net "un4_result[2]" in work.st_mult1(verilog)
	net "un4_result[3]" in work.st_mult1(verilog)
	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)
	net "un4_result[15]" in work.st_mult1(verilog)
	net "un4_result[16]" in work.st_mult1(verilog)
	net "un4_result[17]" in work.st_mult1(verilog)
	net "un4_result[18]" in work.st_mult1(verilog)
	net "un4_result[19]" in work.st_mult1(verilog)
	net "un4_result[20]" in work.st_mult1(verilog)
	net "un4_result[21]" in work.st_mult1(verilog)
	net "un4_result[22]" in work.st_mult1(verilog)
	net "un4_result[23]" in work.st_mult1(verilog)
	net "un4_result[24]" in work.st_mult1(verilog)
	net "un4_result[25]" in work.st_mult1(verilog)
	net "un4_result[26]" in work.st_mult1(verilog)
	net "un4_result[27]" in work.st_mult1(verilog)
	net "un4_result[28]" in work.st_mult1(verilog)
	net "un4_result[29]" in work.st_mult1(verilog)
	net "un4_result[30]" in work.st_mult1(verilog)
	net "un4_result[31]" in work.st_mult1(verilog)
	net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
	net "current_state[0]" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Found combinational loop during mapping at net result[14]
15) instance work.st_mult1(verilog)-result[31:0], output net "result[14]" in work.st_mult1(verilog)
    input nets to instance:
	net "un4_result[0]" in work.st_mult1(verilog)
	net "un4_result[1]" in work.st_mult1(verilog)
	net "un4_result[2]" in work.st_mult1(verilog)
	net "un4_result[3]" in work.st_mult1(verilog)
	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)
	net "un4_result[15]" in work.st_mult1(verilog)
	net "un4_result[16]" in work.st_mult1(verilog)
	net "un4_result[17]" in work.st_mult1(verilog)
	net "un4_result[18]" in work.st_mult1(verilog)
	net "un4_result[19]" in work.st_mult1(verilog)
	net "un4_result[20]" in work.st_mult1(verilog)
	net "un4_result[21]" in work.st_mult1(verilog)
	net "un4_result[22]" in work.st_mult1(verilog)
	net "un4_result[23]" in work.st_mult1(verilog)
	net "un4_result[24]" in work.st_mult1(verilog)
	net "un4_result[25]" in work.st_mult1(verilog)
	net "un4_result[26]" in work.st_mult1(verilog)
	net "un4_result[27]" in work.st_mult1(verilog)
	net "un4_result[28]" in work.st_mult1(verilog)
	net "un4_result[29]" in work.st_mult1(verilog)
	net "un4_result[30]" in work.st_mult1(verilog)
	net "un4_result[31]" in work.st_mult1(verilog)
	net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
	net "current_state[0]" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Found combinational loop during mapping at net result[15]
16) instance work.st_mult1(verilog)-result[31:0], output net "result[15]" in work.st_mult1(verilog)
    input nets to instance:
	net "un4_result[0]" in work.st_mult1(verilog)
	net "un4_result[1]" in work.st_mult1(verilog)
	net "un4_result[2]" in work.st_mult1(verilog)
	net "un4_result[3]" in work.st_mult1(verilog)
	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)
	net "un4_result[15]" in work.st_mult1(verilog)
	net "un4_result[16]" in work.st_mult1(verilog)
	net "un4_result[17]" in work.st_mult1(verilog)
	net "un4_result[18]" in work.st_mult1(verilog)
	net "un4_result[19]" in work.st_mult1(verilog)
	net "un4_result[20]" in work.st_mult1(verilog)
	net "un4_result[21]" in work.st_mult1(verilog)
	net "un4_result[22]" in work.st_mult1(verilog)
	net "un4_result[23]" in work.st_mult1(verilog)
	net "un4_result[24]" in work.st_mult1(verilog)
	net "un4_result[25]" in work.st_mult1(verilog)
	net "un4_result[26]" in work.st_mult1(verilog)
	net "un4_result[27]" in work.st_mult1(verilog)
	net "un4_result[28]" in work.st_mult1(verilog)
	net "un4_result[29]" in work.st_mult1(verilog)
	net "un4_result[30]" in work.st_mult1(verilog)
	net "un4_result[31]" in work.st_mult1(verilog)
	net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
	net "current_state[0]" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Found combinational loop during mapping at net result[16]
17) instance work.st_mult1(verilog)-result[31:0], output net "result[16]" in work.st_mult1(verilog)
    input nets to instance:
	net "un4_result[0]" in work.st_mult1(verilog)
	net "un4_result[1]" in work.st_mult1(verilog)
	net "un4_result[2]" in work.st_mult1(verilog)
	net "un4_result[3]" in work.st_mult1(verilog)
	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)
	net "un4_result[15]" in work.st_mult1(verilog)
	net "un4_result[16]" in work.st_mult1(verilog)
	net "un4_result[17]" in work.st_mult1(verilog)
	net "un4_result[18]" in work.st_mult1(verilog)
	net "un4_result[19]" in work.st_mult1(verilog)
	net "un4_result[20]" in work.st_mult1(verilog)
	net "un4_result[21]" in work.st_mult1(verilog)
	net "un4_result[22]" in work.st_mult1(verilog)
	net "un4_result[23]" in work.st_mult1(verilog)
	net "un4_result[24]" in work.st_mult1(verilog)
	net "un4_result[25]" in work.st_mult1(verilog)
	net "un4_result[26]" in work.st_mult1(verilog)
	net "un4_result[27]" in work.st_mult1(verilog)
	net "un4_result[28]" in work.st_mult1(verilog)
	net "un4_result[29]" in work.st_mult1(verilog)
	net "un4_result[30]" in work.st_mult1(verilog)
	net "un4_result[31]" in work.st_mult1(verilog)
	net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
	net "current_state[0]" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Found combinational loop during mapping at net result[17]
18) instance work.st_mult1(verilog)-result[31:0], output net "result[17]" in work.st_mult1(verilog)
    input nets to instance:
	net "un4_result[0]" in work.st_mult1(verilog)
	net "un4_result[1]" in work.st_mult1(verilog)
	net "un4_result[2]" in work.st_mult1(verilog)
	net "un4_result[3]" in work.st_mult1(verilog)
	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)
	net "un4_result[15]" in work.st_mult1(verilog)
	net "un4_result[16]" in work.st_mult1(verilog)
	net "un4_result[17]" in work.st_mult1(verilog)
	net "un4_result[18]" in work.st_mult1(verilog)
	net "un4_result[19]" in work.st_mult1(verilog)
	net "un4_result[20]" in work.st_mult1(verilog)
	net "un4_result[21]" in work.st_mult1(verilog)
	net "un4_result[22]" in work.st_mult1(verilog)
	net "un4_result[23]" in work.st_mult1(verilog)
	net "un4_result[24]" in work.st_mult1(verilog)
	net "un4_result[25]" in work.st_mult1(verilog)
	net "un4_result[26]" in work.st_mult1(verilog)
	net "un4_result[27]" in work.st_mult1(verilog)
	net "un4_result[28]" in work.st_mult1(verilog)
	net "un4_result[29]" in work.st_mult1(verilog)
	net "un4_result[30]" in work.st_mult1(verilog)
	net "un4_result[31]" in work.st_mult1(verilog)
	net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
	net "current_state[0]" in work.st_mult1(verilog)
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|Found combinational loop during mapping at net result[18]
19) instance work.st_mult1(verilog)-result[31:0], output net "result[18]" in work.st_mult1(verilog)
    input nets to instance:
	net "un4_result[0]" in work.st_mult1(verilog)
	net "un4_result[1]" in work.st_mult1(verilog)
	net "un4_result[2]" in work.st_mult1(verilog)
	net "un4_result[3]" in work.st_mult1(verilog)
	net "un4_result[4]" in work.st_mult1(verilog)
	net "un4_result[5]" in work.st_mult1(verilog)
	net "un4_result[6]" in work.st_mult1(verilog)
	net "un4_result[7]" in work.st_mult1(verilog)
	net "un4_result[8]" in work.st_mult1(verilog)
	net "un4_result[9]" in work.st_mult1(verilog)
	net "un4_result[10]" in work.st_mult1(verilog)
	net "un4_result[11]" in work.st_mult1(verilog)
	net "un4_result[12]" in work.st_mult1(verilog)
	net "un4_result[13]" in work.st_mult1(verilog)
	net "un4_result[14]" in work.st_mult1(verilog)
	net "un4_result[15]" in work.st_mult1(verilog)
	net "un4_result[16]" in work.st_mult1(verilog)
	net "un4_result[17]" in work.st_mult1(verilog)
	net "un4_result[18]" in work.st_mult1(verilog)
	net "un4_result[19]" in work.st_mult1(verilog)
	net "un4_result[20]" in work.st_mult1(verilog)
	net "un4_result[21]" in work.st_mult1(verilog)
	net "un4_result[22]" in work.st_mult1(verilog)
	net "un4_result[23]" in work.st_mult1(verilog)
	net "un4_result[24]" in work.st_mult1(verilog)
	net "un4_result[25]" in work.st_mult1(verilog)
	net "un4_result[26]" in work.st_mult1(verilog)
	net "un4_result[27]" in work.st_mult1(verilog)
	net "un4_result[28]" in work.st_mult1(verilog)
	net "un4_result[29]" in work.st_mult1(verilog)