📄 st_mult1.srd

📁 veilog实现的状态机乘法器.可以参考
💻 SRD
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f "noname"; #file 0
f "d:\program_files\synplify81\fpga_81\lib\altera\altera.v"; #file 1
f "g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v"; #file 2
VNAME 'work.st_mult1.verilog'; # view id 0
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