st_mult1.plg

veilog实现的状态机乘法器.可以参考

@P:  Part : EPF10K10TC144-3
@P:  Worst Slack : 981.380
@P:  st_mult1|clk - Estimated Frequency : 61.3 MHz
@P:  st_mult1|clk - Requested Frequency : 1.0 MHz
@P:  st_mult1|clk - Estimated Period : 16.324
@P:  st_mult1|clk - Requested Period : 1000.000
@P:  st_mult1|clk - Slack : 983.676
@P:  System - Estimated Frequency : 53.7 MHz
@P:  System - Requested Frequency : 1.0 MHz
@P:  System - Estimated Period : 18.620
@P:  System - Requested Period : 1000.000
@P:  System - Slack : 981.380
@P: st_mult1 Part : epf10k10tc144-3
@P: st_mult1 Total LUTs: : 88 of 576 (15%) 
@P: st_mult1 Logic resources : 88 LCs of 576 (15%) 
@P: st_mult1 Register bits : 2
@P: st_mult1 EABs : 0
@P: st_mult1 I/O cells : 67