st_mult1.msg

veilog实现的状态机乘法器.可以参考

@TM:1142648980
@W:  :"":0:0:0:-1|Net current_state_i[0] appears to be a clock source which was not identified. Assuming default frequency. 
@TM:1142604676
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1142604670
@N:  :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":1:7:1:14|Synthesizing module st_mult1
@TM:1142618248
@N: CL201 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":17:1:17:6|M
@TM:1142648974
@W: CG296 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":24:8:24:20|M
@TM:1142618248
@W:  :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|M
@W: BN134 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|M
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|M
@W: CL113 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|M
@W: CL118 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":29:1:29:4|M
@TM:1142648974
@W: CG290 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":33:32:33:44|M
@W: CG290 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":35:32:35:40|M
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":46:11:46:36|M
@TM:1142618248
@W: BN134 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":55:12:55:19|M
@W: BN137 :"g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v":55:12:55:19|M