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<!@TC:1142649438>
#Program: Synplify Pro 8.1
#OS: Windows_NT
<a name=compilerReport1>$ Start of Compile
#Sat Mar 18 10:37:09 2006
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
@I::"D:\Program_Files\synplify81\fpga_81\lib\altera\altera.v"
@I::"G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v"
Verilog syntax check successful!
File G:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v changed - recompiling
Selecting top level module st_mult1
@N: : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:1:7:1:15:@N::@XP_MSG">st_mult1.v(1)</a><!@TM:1142649438> | Synthesizing module st_mult1
<font color=#A52A2A>@W:<a href="@W:CG296:@XP_HELP">CG296</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:24:8:24:21:@W:CG296:@XP_MSG">st_mult1.v(24)</a><!@TM:1142649438> | Incomplete sensitivity list - assuming completeness</font>
<font color=#A52A2A>@W:<a href="@W:CG290:@XP_HELP">CG290</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:35:32:35:41:@W:CG290:@XP_MSG">st_mult1.v(35)</a><!@TM:1142649438> | Referenced variable cheng_shu is not in sensitivity list</font>
<font color=#A52A2A>@W:<a href="@W:CG290:@XP_HELP">CG290</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:33:32:33:45:@W:CG290:@XP_MSG">st_mult1.v(33)</a><!@TM:1142649438> | Referenced variable bei_cheng_shu is not in sensitivity list</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:29:1:29:5:@W:CL118:@XP_MSG">st_mult1.v(29)</a><!@TM:1142649438> | Latch generated from always block for signal result[31:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:29:1:29:5:@W:CL118:@XP_MSG">st_mult1.v(29)</a><!@TM:1142649438> | Latch generated from always block for signal bei_cheng_shu_Temp[31:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:29:1:29:5:@W:CL118:@XP_MSG">st_mult1.v(29)</a><!@TM:1142649438> | Latch generated from always block for signal count[4:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL113:@XP_HELP">CL113</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:29:1:29:5:@W:CL113:@XP_MSG">st_mult1.v(29)</a><!@TM:1142649438> | Feedback mux created for signal ok.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:29:1:29:5:@W:CL118:@XP_MSG">st_mult1.v(29)</a><!@TM:1142649438> | Latch generated from always block for signal ok, probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:29:1:29:5:@W:CL118:@XP_MSG">st_mult1.v(29)</a><!@TM:1142649438> | Latch generated from always block for signal cheng_shu_temp[15:0], probably caused by a missing assignment in an if or case stmt</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:17:1:17:7:@N:CL201:@XP_MSG">st_mult1.v(17)</a><!@TM:1142649438> | Trying to extract state machine for register current_state
Extracted state machine for register current_state
State machine has 4 reachable states with original encodings of:
00
01
10
11
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Mar 18 10:37:11 2006
###########################################################[
Version 8.1
<a name=mapperReport2>Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May 6 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
Warning: Found 37 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:29:1:29:5:@W:BN137:@XP_MSG">st_mult1.v(29)</a><!@TM:1142649438> | Found combinational loop during mapping at net result[0]</font>
1) instance work.st_mult1(verilog)-result[31:0], output net "result[0]" in work.st_mult1(verilog)
input nets to instance:
net "un4_result[0]" in work.st_mult1(verilog)
net "un4_result[1]" in work.st_mult1(verilog)
net "un4_result[2]" in work.st_mult1(verilog)
net "un4_result[3]" in work.st_mult1(verilog)
net "un4_result[4]" in work.st_mult1(verilog)
net "un4_result[5]" in work.st_mult1(verilog)
net "un4_result[6]" in work.st_mult1(verilog)
net "un4_result[7]" in work.st_mult1(verilog)
net "un4_result[8]" in work.st_mult1(verilog)
net "un4_result[9]" in work.st_mult1(verilog)
net "un4_result[10]" in work.st_mult1(verilog)
net "un4_result[11]" in work.st_mult1(verilog)
net "un4_result[12]" in work.st_mult1(verilog)
net "un4_result[13]" in work.st_mult1(verilog)
net "un4_result[14]" in work.st_mult1(verilog)
net "un4_result[15]" in work.st_mult1(verilog)
net "un4_result[16]" in work.st_mult1(verilog)
net "un4_result[17]" in work.st_mult1(verilog)
net "un4_result[18]" in work.st_mult1(verilog)
net "un4_result[19]" in work.st_mult1(verilog)
net "un4_result[20]" in work.st_mult1(verilog)
net "un4_result[21]" in work.st_mult1(verilog)
net "un4_result[22]" in work.st_mult1(verilog)
net "un4_result[23]" in work.st_mult1(verilog)
net "un4_result[24]" in work.st_mult1(verilog)
net "un4_result[25]" in work.st_mult1(verilog)
net "un4_result[26]" in work.st_mult1(verilog)
net "un4_result[27]" in work.st_mult1(verilog)
net "un4_result[28]" in work.st_mult1(verilog)
net "un4_result[29]" in work.st_mult1(verilog)
net "un4_result[30]" in work.st_mult1(verilog)
net "un4_result[31]" in work.st_mult1(verilog)
net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
net "current_state[0]" in work.st_mult1(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:29:1:29:5:@W:BN137:@XP_MSG">st_mult1.v(29)</a><!@TM:1142649438> | Found combinational loop during mapping at net result[1]</font>
2) instance work.st_mult1(verilog)-result[31:0], output net "result[1]" in work.st_mult1(verilog)
input nets to instance:
net "un4_result[0]" in work.st_mult1(verilog)
net "un4_result[1]" in work.st_mult1(verilog)
net "un4_result[2]" in work.st_mult1(verilog)
net "un4_result[3]" in work.st_mult1(verilog)
net "un4_result[4]" in work.st_mult1(verilog)
net "un4_result[5]" in work.st_mult1(verilog)
net "un4_result[6]" in work.st_mult1(verilog)
net "un4_result[7]" in work.st_mult1(verilog)
net "un4_result[8]" in work.st_mult1(verilog)
net "un4_result[9]" in work.st_mult1(verilog)
net "un4_result[10]" in work.st_mult1(verilog)
net "un4_result[11]" in work.st_mult1(verilog)
net "un4_result[12]" in work.st_mult1(verilog)
net "un4_result[13]" in work.st_mult1(verilog)
net "un4_result[14]" in work.st_mult1(verilog)
net "un4_result[15]" in work.st_mult1(verilog)
net "un4_result[16]" in work.st_mult1(verilog)
net "un4_result[17]" in work.st_mult1(verilog)
net "un4_result[18]" in work.st_mult1(verilog)
net "un4_result[19]" in work.st_mult1(verilog)
net "un4_result[20]" in work.st_mult1(verilog)
net "un4_result[21]" in work.st_mult1(verilog)
net "un4_result[22]" in work.st_mult1(verilog)
net "un4_result[23]" in work.st_mult1(verilog)
net "un4_result[24]" in work.st_mult1(verilog)
net "un4_result[25]" in work.st_mult1(verilog)
net "un4_result[26]" in work.st_mult1(verilog)
net "un4_result[27]" in work.st_mult1(verilog)
net "un4_result[28]" in work.st_mult1(verilog)
net "un4_result[29]" in work.st_mult1(verilog)
net "un4_result[30]" in work.st_mult1(verilog)
net "un4_result[31]" in work.st_mult1(verilog)
net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
net "current_state[0]" in work.st_mult1(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:29:1:29:5:@W:BN137:@XP_MSG">st_mult1.v(29)</a><!@TM:1142649438> | Found combinational loop during mapping at net result[2]</font>
3) instance work.st_mult1(verilog)-result[31:0], output net "result[2]" in work.st_mult1(verilog)
input nets to instance:
net "un4_result[0]" in work.st_mult1(verilog)
net "un4_result[1]" in work.st_mult1(verilog)
net "un4_result[2]" in work.st_mult1(verilog)
net "un4_result[3]" in work.st_mult1(verilog)
net "un4_result[4]" in work.st_mult1(verilog)
net "un4_result[5]" in work.st_mult1(verilog)
net "un4_result[6]" in work.st_mult1(verilog)
net "un4_result[7]" in work.st_mult1(verilog)
net "un4_result[8]" in work.st_mult1(verilog)
net "un4_result[9]" in work.st_mult1(verilog)
net "un4_result[10]" in work.st_mult1(verilog)
net "un4_result[11]" in work.st_mult1(verilog)
net "un4_result[12]" in work.st_mult1(verilog)
net "un4_result[13]" in work.st_mult1(verilog)
net "un4_result[14]" in work.st_mult1(verilog)
net "un4_result[15]" in work.st_mult1(verilog)
net "un4_result[16]" in work.st_mult1(verilog)
net "un4_result[17]" in work.st_mult1(verilog)
net "un4_result[18]" in work.st_mult1(verilog)
net "un4_result[19]" in work.st_mult1(verilog)
net "un4_result[20]" in work.st_mult1(verilog)
net "un4_result[21]" in work.st_mult1(verilog)
net "un4_result[22]" in work.st_mult1(verilog)
net "un4_result[23]" in work.st_mult1(verilog)
net "un4_result[24]" in work.st_mult1(verilog)
net "un4_result[25]" in work.st_mult1(verilog)
net "un4_result[26]" in work.st_mult1(verilog)
net "un4_result[27]" in work.st_mult1(verilog)
net "un4_result[28]" in work.st_mult1(verilog)
net "un4_result[29]" in work.st_mult1(verilog)
net "un4_result[30]" in work.st_mult1(verilog)
net "un4_result[31]" in work.st_mult1(verilog)
net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
net "current_state[0]" in work.st_mult1(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:29:1:29:5:@W:BN137:@XP_MSG">st_mult1.v(29)</a><!@TM:1142649438> | Found combinational loop during mapping at net result[3]</font>
4) instance work.st_mult1(verilog)-result[31:0], output net "result[3]" in work.st_mult1(verilog)
input nets to instance:
net "un4_result[0]" in work.st_mult1(verilog)
net "un4_result[1]" in work.st_mult1(verilog)
net "un4_result[2]" in work.st_mult1(verilog)
net "un4_result[3]" in work.st_mult1(verilog)
net "un4_result[4]" in work.st_mult1(verilog)
net "un4_result[5]" in work.st_mult1(verilog)
net "un4_result[6]" in work.st_mult1(verilog)
net "un4_result[7]" in work.st_mult1(verilog)
net "un4_result[8]" in work.st_mult1(verilog)
net "un4_result[9]" in work.st_mult1(verilog)
net "un4_result[10]" in work.st_mult1(verilog)
net "un4_result[11]" in work.st_mult1(verilog)
net "un4_result[12]" in work.st_mult1(verilog)
net "un4_result[13]" in work.st_mult1(verilog)
net "un4_result[14]" in work.st_mult1(verilog)
net "un4_result[15]" in work.st_mult1(verilog)
net "un4_result[16]" in work.st_mult1(verilog)
net "un4_result[17]" in work.st_mult1(verilog)
net "un4_result[18]" in work.st_mult1(verilog)
net "un4_result[19]" in work.st_mult1(verilog)
net "un4_result[20]" in work.st_mult1(verilog)
net "un4_result[21]" in work.st_mult1(verilog)
net "un4_result[22]" in work.st_mult1(verilog)
net "un4_result[23]" in work.st_mult1(verilog)
net "un4_result[24]" in work.st_mult1(verilog)
net "un4_result[25]" in work.st_mult1(verilog)
net "un4_result[26]" in work.st_mult1(verilog)
net "un4_result[27]" in work.st_mult1(verilog)
net "un4_result[28]" in work.st_mult1(verilog)
net "un4_result[29]" in work.st_mult1(verilog)
net "un4_result[30]" in work.st_mult1(verilog)
net "un4_result[31]" in work.st_mult1(verilog)
net "un1_cheng_shu_temp_1" in work.st_mult1(verilog)
net "current_state[0]" in work.st_mult1(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="g:\taoyuhui\synplifywork_new\statemachine_mult\st_mult1.v:29:1:29:5:@W:BN137:@XP_MSG">st_mult1.v(29)</a><!@TM:1142649438> | Found combinational loop during mapping at net result[4]</font>
5) instance work.st_mult1(verilog)-result[31:0], output net "result[4]" in work.st_mult1(verilog)
input nets to instance:
net "un4_result[0]" in work.st_mult1(verilog)
net "un4_result[1]" in work.st_mult1(verilog)
net "un4_result[2]" in work.st_mult1(verilog)
net "un4_result[3]" in work.st_mult1(verilog)
net "un4_result[4]" in work.st_mult1(verilog)
net "un4_result[5]" in work.st_mult1(verilog)
net "un4_result[6]" in work.st_mult1(verilog)
net "un4_result[7]" in work.st_mult1(verilog)
net "un4_result[8]" in work.st_mult1(verilog)
net "un4_result[9]" in work.st_mult1(verilog)
net "un4_result[10]" in work.st_mult1(verilog)
net "un4_result[11]" in work.st_mult1(verilog)
net "un4_result[12]" in work.st_mult1(verilog)
net "un4_result[13]" in work.st_mult1(verilog)
net "un4_result[14]" in work.st_mult1(verilog)
net "un4_result[15]" in work.st_mult1(verilog)
net "un4_result[16]" in work.st_mult1(verilog)
net "un4_result[17]" in work.st_mult1(verilog)
net "un4_result[18]" in work.st_mult1(verilog)
net "un4_result[19]" in work.st_mult1(verilog)
net "un4_result[20]" in work.st_mult1(verilog)
net "un4_result[21]" in work.st_mult1(verilog)
net "un4_result[22]" in work.st_mult1(verilog)
net "un4_result[23]" in work.st_mult1(verilog)
net "un4_result[24]" in work.st_mult1(verilog)
net "un4_result[25]" in work.st_mult1(verilog)
net "un4_result[26]" in work.st_mult1(verilog)
net "un4_result[27]" in work.st_mult1(verilog)
net "un4_result[28]" in work.st_mult1(verilog)
net "un4_result[29]" in work.st_mult1(verilog)
net "un4_result[30]" in work.st_mult1(verilog)
net "un4_result[31]" in work.st_mult1(verilog)
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