📄 jiaotd.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
---------------------------------
ENTITY jiaotd IS
PORT(
clk : IN STD_LOGIC;
lr,lg,ly : OUT STD_LOGIC_VECTOR(2 downto 1);
led : OUT STD_LOGIC_VECTOR(6 downto 0);
sel2 : BUFFER STD_LOGIC);
END jiaotd;
--------------------------------
ARCHITECTURE a OF jiaotd IS
TYPE STATES IS (ST0,ST1,ST2,ST3,ST4,ST5); --STATE=0: SN GREEN
-- =1: SN GREEN FLASH
-- =2: SN YELLOW
-- =3: EW GREEN
-- =4: EW GREEN FLASH
-- =5: EW YELLOW
SIGNAL C_STATE,N_STATE:STATES:=ST0;
SIGNAL CNT1: STD_LOGIC_VECTOR(9 downto 0); --GET 1HZ
SIGNAL CNT2,CNT3,DP,DP1,DP2: STD_LOGIC_VECTOR(3 downto 0);--CNT2 16 RED; CNT3 10 GREEN
SIGNAL CNT9: STD_LOGIC;
BEGIN
PROCESS (clk) --GET 1HZ
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
CNT1<=CNT1+1;
SEL2<=NOT(SEL2);
END IF;
END PROCESS;
cnt9<=cnt1(9);
PROCESS (CNT9) --RED/GREEN TIME CNT
BEGIN
IF (cnt9'EVENT AND cnt9='1') THEN
CNT2<=CNT2-1;
IF ((C_STATE=ST0) OR (C_STATE=ST3)) THEN
IF CNT3 /= 0 THEN
CNT3<=CNT3-1;
ELSE
CNT3<="1010";
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (C_STATE,CNT2) --N_STATE
BEGIN
CASE C_STATE IS
WHEN ST0 =>IF CNT2="0101" THEN N_STATE<=ST1;
ELSE N_STATE<=ST0;
END IF;
LG(1)<='1';LY(1)<='0';LR(1)<='0';
LG(2)<='0';LY(2)<='0';LR(2)<='1';
DP1<=CNT3;DP2<=CNT2;
WHEN ST1 =>IF CNT2="0010" THEN N_STATE<=ST2;
ELSE N_STATE<=ST1;
END IF;
LG(1)<=CNT1(9);LY(1)<='0';LR(1)<='0';
LG(2)<='0';LY(2)<='0';LR(2)<='1';
DP1<=CNT3;DP2<=CNT2;
WHEN ST2 =>IF CNT2="0000" THEN N_STATE<=ST3;
ELSE N_STATE<=ST2;
END IF;
LG(1)<='0';LY(1)<='1';LR(1)<='0';
LG(2)<='0';LY(2)<='0';LR(2)<='1';
DP1<=CNT3;DP2<=CNT2;
WHEN ST3 =>IF CNT2="0101" THEN N_STATE<=ST4;
ELSE N_STATE<=ST3;
END IF;
LG(1)<='0';LY(1)<='0';LR(1)<='1';
LG(2)<='1';LY(2)<='0';LR(2)<='0';
DP1<=CNT2;DP2<=CNT3;
WHEN ST4 =>IF CNT2="0010" THEN N_STATE<=ST5;
ELSE N_STATE<=ST4;
END IF;
LG(1)<='0';LY(1)<='0';LR(1)<='1';
LG(2)<=CNT1(9);LY(2)<='0';LR(2)<='0';
DP1<=CNT2;DP2<=CNT3;
WHEN ST5 =>IF CNT2="0000" THEN N_STATE<=ST0;
ELSE N_STATE<=ST5;
END IF;
LG(1)<='0';LY(1)<='0';LR(1)<='1';
LG(2)<='0';LY(2)<='1';LR(2)<='0';
DP1<=CNT2;DP2<=CNT3;
WHEN OTHERS => N_STATE<=ST0;
END CASE;
END PROCESS;
PROCESS (clk) --STATE SWITCH
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
C_STATE<=N_STATE;
END IF;
END PROCESS;
PROCESS (SEL2) --SWITCH DP
BEGIN
CASE SEL2 IS
WHEN '1' =>DP<=DP1;
WHEN '0' =>DP<=DP2;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
PROCESS( DP )
BEGIN
CASE DP IS
WHEN "0000" => led<= "0111111";
WHEN "0001" => led<= "0000110";
WHEN "0010" => led<= "1011011";
WHEN "0011" => led<= "1001111";
WHEN "0100" => led<= "1100110";
WHEN "0101" => led<= "1101101";
WHEN "0110" => led<= "1111101";
WHEN "0111" => led<= "0000111";
WHEN "1000" => led<= "1111111";
WHEN "1001" => led<= "1101111";
WHEN "1010" => led<= "1110111";
WHEN "1011" => led<= "1111100";
WHEN "1100" => led<= "0111001";
WHEN "1101" => led<= "1011110";
WHEN "1110" => led<= "1111001";
WHEN "1111" => led<= "1110001";
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END a;
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