usbf_transeiver.v

经过门级网单验证的USB2.0 IP核 RTL代码

//usbf_transeiver
`include "usbf_defines.v"

module usbf_transeiver(
		/* clk_i, rst_i,wb_addr_i, wb_data_i, wb_data_o,
		wb_ack_o, wb_we_i, wb_stb_i, wb_cyc_i,*/
		inta_o, intb_o,
		dma_req_o, dma_ack_i, susp_o, resume_req_i,

		// AHB Interface
		hsel, haddr, hwrite, htrans, hsize, hburst, hwdata,
		hresetn, hclk, hready_resp, hresp, hrdata, 

		// UTMI Interface
		phy_clk_pad_i, phy_rst_pad_o,

		/*DataOut_pad_o, TxValid_pad_o, TxReady_pad_i,
		RxValid_pad_i, RxActive_pad_i, RxError_pad_i,
		DataIn_pad_i,  LineState_pad_i,*/

		XcvSelect_pad_o, TermSel_pad_o,	SuspendM_pad_o,

		OpMode_pad_o, usb_vbus_pad_i,
		VControl_Load_pad_o, VControl_pad_o, VStatus_pad_i,

		// Transciever Interface
		//txdp, txdn, txoe,
		//rxd, rxdp, rxdn,
		vp,vm,oe,phy_tx_mode,usb_rst

		// Buffer Memory Interface
		//sram_adr_o, sram_data_i, sram_data_o, sram_re_o, sram_we_o

		);

parameter	SSRAM_HADR = `USBF_SSRAM_HADR;
//input		clk_i;
//input		rst_i;
/*input	[`USBF_UFC_HADR:0]	wb_addr_i;
input	[31:0]	wb_data_i;
output	[31:0]	wb_data_o;
output		wb_ack_o;
input		wb_we_i;
input		wb_stb_i;
input		wb_cyc_i;
*/
// Transciever Interface
//output		txdp, txdn, txoe;
//input		rxd, rxdp, rxdn;
inout vp,vm,oe;
input phy_tx_mode;
output usb_rst;
// AHB Interface
input hsel;
input [`USBF_UFC_HADR:0] haddr;				// [`USBF_UFC_HADR:0]
input hwrite;
input [1:0] htrans;
input [2:0] hsize;				// =2
input [2:0] hburst;
input [31:0] hwdata;			// [31:0]
input hresetn;
input hclk;


output hready_resp;
output [1:0] hresp;
output [31:0] hrdata;			// [31:0]

output		inta_o;
output		intb_o;
output	[15:0]	dma_req_o;
input	[15:0]	dma_ack_i;
output		susp_o;
input		resume_req_i;

input		phy_clk_pad_i;
output		phy_rst_pad_o;



output		XcvSelect_pad_o;
output		TermSel_pad_o;
output		SuspendM_pad_o;
output	[1:0]	OpMode_pad_o;
input		usb_vbus_pad_i;
output		VControl_Load_pad_o;
output	[3:0]	VControl_pad_o;
input	[7:0]	VStatus_pad_i;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//

//Buffer Interface
wire	[SSRAM_HADR:0]	sram_adr_o;
wire	[31:0]	sram_data_i;
wire	[31:0]	sram_data_o;
wire		sram_re_o;
wire		sram_we_o;


// UTMI Interface
wire	[7:0]	rx_data;
wire		rx_valid, rx_active, rx_err;
wire	[7:0]	tx_data;
wire		tx_valid;
wire		tx_ready;
wire		tx_first;
wire		tx_valid_last;


wire	[7:0]	DataOut_pad_o;
wire		TxValid_pad_o;
wire		TxReady_pad_i;

wire	[7:0]	DataIn_pad_i;
wire		RxValid_pad_i;
wire		RxActive_pad_i;
wire		RxError_pad_i;
wire	[1:0]	LineState_pad_i;



// Misc UTMI USB status
wire		mode_hs;	// High Speed Mode
wire		usb_reset;	// USB Reset
wire		usb_suspend;	// USB Sleep
wire		usb_attached;	// Attached to USB
wire		resume_req;	// Resume Request

// Memory Arbiter Interface
wire	[SSRAM_HADR:0]	madr;		// word address
wire	[31:0]	mdout;
wire	[31:0]	mdin;
wire		mwe;
wire		mreq;
wire		mack;
wire		rst;

// AHB Memory interface
wire	[`USBF_UFC_HADR:0]	ma_adr;
wire	[31:0]	ma2wb_d;
wire	[31:0]	wb2ma_d;
wire		ma_we;
wire		ma_req;
wire		ma_ack;

//AHB Register File interface
wire		rf_re;
wire		rf_we;
wire	[31:0]	wb2rf_d;
wire	[31:0]	rf2wb_d;

// Internal Register File Interface
wire	[6:0]	funct_adr;	// This functions address (set by controller)
wire	[31:0]	idin;		// Data Input
wire	[3:0]	ep_sel;		// Endpoint Number Input
wire		match;		// Endpoint Matched
wire		dma_in_buf_sz1;
wire		dma_out_buf_avail;
wire		buf0_rl;	// Reload Buf 0 with original values
wire		buf0_set;	// Write to buf 0
wire		buf1_set;	// Write to buf 1
wire		uc_bsel_set;	// Write to the uc_bsel field
wire		uc_dpd_set;	// Write to the uc_dpd field
wire		int_buf1_set;	// Set buf1 full/empty interrupt
wire		int_buf0_set;	// Set buf0 full/empty interrupt
wire		int_upid_set;	// Set unsupported PID interrupt
wire		int_crc16_set;	// Set CRC16 error interrupt
wire		int_to_set;	// Set time out interrupt
wire		int_seqerr_set;	// Set PID sequence error interrupt
wire		out_to_small;	// OUT packet was to small for DMA operation
wire	[31:0]	csr;		// Internal CSR Output
wire	[31:0]	buf0;		// Internal Buf 0 Output
wire	[31:0]	buf1;		// Internal Buf 1 Output
wire	[31:0]	frm_nat;	// Frame Number and Time Register
wire		nse_err;	// No Such Endpoint Error
wire		pid_cs_err;	// PID CS error
wire		crc5_err;	// CRC5 Error
wire		rf_resume_req;	// Resume Request From main CSR

reg		susp_o;
reg	[1:0]	LineState_r;	// Added to make a full synchronizer
reg	[7:0]	VStatus_r;	// Added to make a full synchronizer

///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign rst = hresetn;
assign phy_rst_pad_o = hresetn;
assign resume_req = resume_req_i;

always @(posedge hclk)
	susp_o <= usb_suspend;

always @(posedge phy_clk_pad_i)		// First Stage Synchronizer
	LineState_r <= LineState_pad_i;

always @(posedge phy_clk_pad_i)		// First Stage Synchronizer
	VStatus_r <= VStatus_pad_i;

///////////////////////////////////////////////////////////////////
//
// Module Instantiations
//

reg		resume_req_r;
reg		suspend_clr_wr;
wire		suspend_clr;

always @(posedge hclk)
	suspend_clr_wr <= suspend_clr;

`ifdef USBF_ASYNC_RESET
always @(posedge hclk or negedge rst)
`else
always @(posedge hclk)
`endif
	if(!rst)		resume_req_r <= 1'b0;
	else
	if(suspend_clr_wr)	resume_req_r <= 1'b0;
	else
	if(resume_req)		resume_req_r <= 1'b1;
//Buffer Interface

rf_spsram_32k_32  m_buf(
	   .Q (sram_data_i),
	   .CLK (phy_clk_pad_i),
	   .CEN (~sram_re_o),
	   .WEN (~sram_we_o),
	   .A (sram_adr_o),
	   .D (sram_data_o)
	);


//PHY Interface
usbf_phy	PHY(
		.clk(phy_clk_pad_i), 
		.rst(rst), 
		.phy_tx_mode(phy_tx_mode), 
		.usb_rst(usb_rst),

		//.txdp(txdp), 
		//.txdn(txdn), 
		//.txoe(txoe),	
		//.rxd(rxd), 
		///.rxdp(rxdp), 
		//.rxdn(rxdn),
		.vp(vp),
		.vm(vm),
		.oe(oe),

		.DataOut_i(DataOut_pad_o), 
		.TxValid_i(TxValid_pad_o), 
		.TxReady_o(TxReady_pad_i), 
		.RxValid_o(RxValid_pad_i),
		.RxActive_o(RxActive_pad_i), 
		.RxError_o(RxError_pad_i), 
		.DataIn_o(DataIn_pad_i), 
		.LineState_o(LineState_pad_i)

		);

// UTMI Interface
usbf_utmi_if	Utmi_Interface(
		.phy_clk(	phy_clk_pad_i	),
		.rst(		rst		),
		.DataOut(	DataOut_pad_o	),
		.TxValid(	TxValid_pad_o	),
		.TxReady(	TxReady_pad_i	),
		.RxValid(	RxValid_pad_i	),
		.RxActive(	RxActive_pad_i	),
		.RxError(	RxError_pad_i	),
		.DataIn(	DataIn_pad_i	),
		.XcvSelect(	XcvSelect_pad_o	),
		.TermSel(	TermSel_pad_o	),
		.SuspendM(	SuspendM_pad_o	),
		.LineState(	LineState_pad_i	),
		.OpMode(	OpMode_pad_o	),
		.usb_vbus(	usb_vbus_pad_i	),
		.rx_data(	rx_data		),
		.rx_valid(	rx_valid	),
		.rx_active(	rx_active	),
		.rx_err(	rx_err		),
		.tx_data(	tx_data		),
		.tx_valid(	tx_valid	),
		.tx_valid_last(	tx_valid_last	),
		.tx_ready(	tx_ready	),
		.tx_first(	tx_first	),
		.mode_hs(	mode_hs		),
		.usb_reset(	usb_reset	),
		.usb_suspend(	usb_suspend	),
		.usb_attached(	usb_attached	),
		.resume_req(	resume_req_r	),
		.suspend_clr(	suspend_clr	)
		);

// Protocol Layer
usbf_pl #(SSRAM_HADR)
	ProtocolLayer(	.clk(			phy_clk_pad_i		),
		.rst(			rst			),
		.rx_data(		rx_data			),
		.rx_valid(		rx_valid		),
		.rx_active(		rx_active		),
		.rx_err(		rx_err			),
		.tx_data(		tx_data			),
		.tx_valid(		tx_valid		),
		.tx_valid_last(		tx_valid_last		),
		.tx_ready(		tx_ready		),