uart_tx.tdf

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TITLE "Compact UART, Transmitter Module"; 
-- Version 1.0, April 4th 1997
-- Copyright Rune Baeverrud
-- You may use or distribute this LPM function freely,
-- provided you do not remove this copyright notice.
-- You can download it from www.fpga.com.cn or www.pld.com.cn

PARAMETERS
(
  MSB_FIRST = "YES",
  STOP_BITS = 1,
  WIDTH = 8
);

SUBDESIGN uart_tx
(
  SysClk              : INPUT;
  BaudGen             : INPUT;
  Load                : INPUT;
  D[WIDTH-1..0] : INPUT;

  TxD                 : OUTPUT;
  TxBusy              : OUTPUT; 
)

VARIABLE
  dbcount[CEIL(LOG2(WIDTH+STOP_BITS+1))-1..0]: DFF; 
  InShift[WIDTH+1..0]: DFF;
  Ss: MACHINE WITH STATES (idle, wait, send);
  DTMP[WIDTH-1..0]: NODE;

BEGIN
  ASSERT (MSB_FIRST == "YES" OR MSB_FIRST == "NO")
	REPORT "Value of MSB_FIRST parameter (%) must be ""YES"" OR ""NO"""
    MSB_FIRST
	SEVERITY ERROR;

  ASSERT (WIDTH > 1)
	REPORT "Value of WIDTH parameter (%) must be equal to or greater than 2"
    WIDTH
	SEVERITY ERROR;

  ASSERT (STOP_BITS > 0)
	REPORT "Value of STOP_BITS parameter (%) must be equal to or greater than 1"
    STOP_BITS
	SEVERITY ERROR;

  dbcount[].clk = SysClk;
  InShift[].clk = SysClk;
  Ss.clk = SysClk;

-- This section controls the state machine
  CASE Ss IS
  WHEN idle =>
    IF Load THEN
      Ss = wait;
    ELSE
      Ss = idle;
    END IF;
  WHEN wait =>
    IF BaudGen THEN
      Ss = send;
    ELSE
      Ss = wait;
    END IF;
  WHEN send =>
    IF dbcount[] != 0 THEN
	    Ss = wait;
	  ELSE
	    Ss = idle;
    END IF;
  WHEN OTHERS =>
    Ss = idle;
  END CASE;

-- Controls the TxD output
  TxD = InShift[WIDTH+1];

-- Controls the TxBusy output
  IF Ss != idle THEN
    TxBusy = VCC;
  END IF;

-- Keeps track of how many bits has been sent
  CASE Ss IS
  WHEN idle =>
    dbcount[] = WIDTH+STOP_BITS;
  WHEN send =>
    dbcount[] = dbcount[] - 1;
  WHEN OTHERS =>
    dbcount[] = dbcount[];
  END CASE;
    
-- Controls the input shift register
  CASE Ss IS
  WHEN idle =>
    IF MSB_FIRST == "YES" GENERATE
      DTMP[] = D[];
    ELSE GENERATE
			FOR each_bit IN 0 TO WIDTH-1 GENERATE
        DTMP[WIDTH -1 -each_bit] = D[each_bit];	
      END GENERATE;
    END GENERATE;
    InShift[] = (0,1,DTMP[]);
  WHEN send =>
    InShift[WIDTH+1..1] = InShift[WIDTH..0];
	  InShift[0] = GND;
  WHEN OTHERS =>
    InShift[] = InShift[];
  END CASE;

 END;