corner.tdf

一些vhdl源代码 一些vhdl代码

TITLE "Corner Bender"; 
-- Version 1.0, June 30th 1997
-- Copyright Iain Rankin
--
-- You may use or distribute this LPM function freely,
-- provided you do not remove this copyright notice.
-- You can download it from www.fpga.com.cn or www.pld.com.cn

PARAMETERS
(
	WIDTH = 1,
	PIPE_DIV_N = "NO",
	PIPE_OP	= "NO"
);


SUBDESIGN corner
(
	clk					: INPUT;
	aclr				: INPUT;
	Enable				: INPUT;
	mode				: INPUT;

	din[WIDTH..1]		: INPUT;

	dout[WIDTH..1]		: OUTPUT;
)

VARIABLE

IF (WIDTH > 0) GENERATE
	array[WIDTH..1][WIDTH..1]	: DFFE;

	IF (PIPE_DIV_N == "YES") GENERATE
		in_buf[WIDTH..1]	: DFFE;
	ELSE GENERATE
		in_buf[WIDTH..1]	: WIRE;
	END GENERATE;	

	IF (PIPE_OP == "YES") GENERATE
		out_buf[WIDTH..1]	: DFFE;
	ELSE GENERATE
		out_buf[WIDTH..1]	: WIRE;
	END GENERATE;

END GENERATE;

BEGIN

ASSERT (PIPE_DIV_N == "YES" # PIPE_DIV_N == "NO")
REPORT "Illegal value for PIPE_DIV_N parameter (%) -- value must be YES or NO" 
	PIPE_DIV_N
	SEVERITY ERROR;

ASSERT (PIPE_OP == "YES" # PIPE_OP == "NO")
REPORT "Illegal value for PIPE_OP parameter (%) -- value must be YES or NO" 
	PIPE_OP
	SEVERITY ERROR;

ASSERT (WIDTH > 0)
	REPORT "Value of WIDTH parameter (%) must be equal to or greater than 1" 
	WIDTH
	SEVERITY ERROR;

	IF (PIPE_DIV_N == "YES") GENERATE
		in_buf[].clk = clk;
		in_buf[].clrn = !aclr;
		in_buf[].ena = Enable;
	END GENERATE;

	in_buf[] = din[];	% Pipeline or WIRE input %

	array[][].clk = clk;
	array[][].clrn = !aclr;
	array[][].ena = Enable;

	FOR xscan IN 1 TO WIDTH GENERATE
		FOR yscan IN 1 TO WIDTH GENERATE
			IF (xscan == 1) GENERATE
				IF (yscan == 1) GENERATE
					array[1][yscan] = (in_buf[1] & mode) # (in_buf[1] & !mode);
				ELSE GENERATE
					array[1][yscan] = (array[1][yscan-1] & mode) # (in_buf[yscan] & !mode);
				END GENERATE;
			ELSE GENERATE
				IF ( yscan == 1) GENERATE
					array[xscan][1] = (in_buf[xscan] & mode) # (array[xscan-1][1] & !mode);
				ELSE GENERATE
					array[xscan][yscan] = (array[xscan][yscan-1] & mode) # (array[xscan-1][yscan] & !mode);
				END GENERATE;					
			END GENERATE;		
		END GENERATE;
	END GENERATE;

	IF (PIPE_OP == "YES" ) GENERATE
		out_buf[].clk = clk;
		out_buf[].clrn = !aclr;
		out_buf[].ena = Enable;		
	END GENERATE;

	out_buf[] = (array[WIDTH][] & !mode) # (array[][WIDTH] & mode); 
	dout[] = out_buf[]; % Pipeline or WIRE output %
END;