test_sim_dp2.vhd

该文件时RAM的源文件和测试文件以及仿真文件

----------------------------------------------------------------------------
----------------------------------------------------------------------------
--  The Free IP Project
--  VHDL Free-RAM Core
--  (c) 1999, The Free IP Project and David Kessner
--
--
--  FREE IP GENERAL PUBLIC LICENSE
--  TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
--
--  1.  You may copy and distribute verbatim copies of this core, as long
--      as this file, and the other associated files, remain intact and
--      unmodified.  Modifications are outlined below.  
--  2.  You may use this core in any way, be it academic, commercial, or
--      military.  Modified or not.  
--  3.  Distribution of this core must be free of charge.  Charging is
--      allowed only for value added services.  Value added services
--      would include copying fees, modifications, customizations, and
--      inclusion in other products.
--  4.  If a modified source code is distributed, the original unmodified
--      source code must also be included (or a link to the Free IP web
--      site).  In the modified source code there must be clear
--      identification of the modified version.
--  5.  Visit the Free IP web site for additional information.
--      http://www.free-ip.com
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;


entity ram_test is
end ram_test;


architecture arch_ram_test of ram_test is
  signal reset		:std_logic := '1';
  signal mask		:std_logic_vector (31 downto 0);
  type STATES is (WRITE, READ);

  signal clk1		:std_logic := '1';
  signal state1		:states;
  signal state_reg1	:states;
  signal addr1		:std_logic_vector (12 downto 0);
  signal addr_in1	:std_logic_vector (addr1'high+1 downto 0);
  signal din1		:std_logic_vector (7 downto 0);
  signal dout1		:std_logic_vector (din1'range);
  signal write_enable1	:std_logic;
  signal rand1_1	:std_logic_vector (mask'range);
  signal rand2_1	:std_logic_vector (mask'range);
  signal rand2_reg_1 	:std_logic_vector (mask'range);
  signal addr_top1	:std_logic;
  signal failure1 	:std_logic;

  signal clk2		:std_logic := '1';
  signal state2		:states;
  signal state_reg2	:states;
  signal addr2		:std_logic_vector (addr1'range);
  signal addr_in2	:std_logic_vector (addr1'high+1 downto 0);
  signal din2		:std_logic_vector (din1'range);
  signal dout2		:std_logic_vector (din1'range);
  signal write_enable2	:std_logic;
  signal rand1_2	:std_logic_vector (mask'range);
  signal rand2_2	:std_logic_vector (mask'range);
  signal rand2_reg_2 	:std_logic_vector (mask'range);
  signal addr_top2	:std_logic;
  signal failure2	:std_logic;

  signal addr_max	:std_logic_vector (addr1'range);

begin
  reset <= '1' after 0 ns, '0' after 125 ns;
  mask <= "10100011000000000000000000000000";  -- 0xA3000000
  addr_max <= (others=>'1');


  process (clk1)
  begin
    if clk1='1' then
      clk1 <= '0' after 20 ns, '1' after 40 ns;
    end if;
  end process;

  process (clk2)
  begin
    if clk2='1' then
      clk2 <= '0' after 21 ns, '1' after 42 ns;
    end if;
  end process;



  -- The address counter
  process (reset, clk1)
  begin
    if reset='1' then
      addr1 <= (others=>'0');
    elsif clk1'event and clk1='1' then
      addr1 <= addr1 + 1;
    end if;
  end process;

  process (reset, clk2)
  begin
    if reset='1' then
      addr2 <= (others=>'0');
    elsif clk2'event and clk2='1' then
      addr2 <= addr2 + 1;
    end if;
  end process;


  -- The addr_top signal
  addr_top1 <= '1' when addr1=addr_max else '0';
  addr_top2 <= '1' when addr2=addr_max else '0';
  

  -- The state machine
  process (reset, clk1)
  begin
    if reset='1' then
      state1 <= WRITE;
    elsif clk1'event and clk1='1' then
      case state1 is
        when WRITE =>
            if addr_top1='1' then
              state1 <= READ;
            end if;
            
        when READ =>
            if addr_top1='1' then
              state1 <= WRITE;
            end if;
            
        when others =>
            state1 <= WRITE;
      end case;
    end if;
  end process;


  process (reset, clk2)
  begin
    if reset='1' then
      state2 <= WRITE;
    elsif clk2'event and clk2='1' then
      case state2 is
        when WRITE =>
            if addr_top2='1' then
              state2 <= READ;
            end if;
            
        when READ =>
            if addr_top2='1' then
              state2 <= WRITE;
            end if;
            
        when others =>
            state2 <= WRITE;
      end case;
    end if;
  end process;


  -- Generate a delayed version of state
  process (reset, clk1)
  begin
    if reset='1' then
      state_reg1 <= WRITE;
    elsif clk1'event and clk1='1' then
      state_reg1 <= state1;
    end if;
  end process;

  process (reset, clk2)
  begin
    if reset='1' then
      state_reg2 <= WRITE;
    elsif clk2'event and clk2='1' then
      state_reg2 <= state2;
    end if;
  end process;


  -- The write data generator
  process (reset, clk1)
  begin
    if reset='1' then
      rand1_1 <= (others => '1');
    elsif clk1'event and clk1='1' then
      if state1=WRITE then
        if rand1_1(0)='1' then
          rand1_1 <= ("0" & rand1_1(rand1_1'high downto 1)) xor mask;
        else
          rand1_1 <= ("0" & rand1_1(rand1_1'high downto 1));
        end if;
      end if;
    end if;
  end process;

  addr_in1 <= "0" & addr1;
  din1 <= rand1_1(din1'range);


  process (reset, clk2)
  begin
    if reset='1' then
      rand1_2 <= (others => '1');
    elsif clk2'event and clk2='1' then
      if state2=WRITE then
        if rand1_2(0)='1' then
          rand1_2 <= ("0" & rand1_2(rand1_2'high downto 1)) xor mask;
        else
          rand1_2 <= ("0" & rand1_2(rand1_2'high downto 1));
        end if;
      end if;
    end if;
  end process;

  addr_in2 <= "1" & addr2;
  din2 <= rand1_2(din2'range);


  -- The READ data generator
  process (reset, clk1)
  begin
    if reset='1' then
      rand2_1 <= (others => '1');
      rand2_reg_1 <= (others => '1');
    elsif clk1'event and clk1='1' then
      rand2_reg_1 <= rand2_1;
      
      if state1=READ then
        if rand2_1(0)='1' then
          rand2_1 <= ("0" & rand2_1(rand2_1'high downto 1)) xor mask;
        else
          rand2_1 <= ("0" & rand2_1(rand2_1'high downto 1));
        end if;
      end if;
    end if;
  end process;

  process (reset, clk2)
  begin
    if reset='1' then
      rand2_2 <= (others => '1');
      rand2_reg_2 <= (others => '1');
    elsif clk2'event and clk2='1' then
      rand2_reg_2 <= rand2_2;
      
      if state2=READ then
        if rand2_2(0)='1' then
          rand2_2 <= ("0" & rand2_2(rand2_2'high downto 1)) xor mask;
        else
          rand2_2 <= ("0" & rand2_2(rand2_2'high downto 1));
        end if;
      end if;
    end if;
  end process;


  -- Write Enable
  process (reset, clk1)
  begin
    if reset='1' then
      write_enable1 <= '1';
    elsif clk1'event and clk1='1' then
      if addr_top1='1' then
        if state1=READ then
          write_enable1 <= '1';
        else
          write_enable1 <= '0';
        end if;
      elsif state1=WRITE then
        write_enable1 <= '1';
      else
        write_enable1 <= '0';
      end if;
    end if;
  end process;

  process (reset, clk2)
  begin
    if reset='1' then
      write_enable2 <= '1';
    elsif clk2'event and clk2='1' then
      if addr_top2='1' then
        if state2=READ then
          write_enable2 <= '1';
        else
          write_enable2 <= '0';
        end if;
      elsif state2=WRITE then
        write_enable2 <= '1';
      else
        write_enable2 <= '0';
      end if;
    end if;
  end process;


  -- The RAM under test
  U1: ram_dp2
  	generic map (addr_bits => addr_in1'high+1,
  	             data_bits => din1'high+1,
  	             block_type => 0)
  	port map (reset,
                  clk1, write_enable1, addr_in1, din1, dout1,
                  clk2, write_enable2, addr_in2, din2, dout2);

  -- Generate the failure signal
  process (reset, clk1)
  begin
    if reset='1' then
      failure1 <= '0';
    elsif clk1'event and clk1='1' then
      if failure1='0' then
        if state_reg1=READ then
          if dout1/=rand2_reg_1(dout2'range) then
            failure1 <= '1';
            assert 1=0
            report "Error in port 1."
                    severity failure;           
          end if;
        end if;
      end if;
    end if;
  end process;

  process (reset, clk2)
  begin
    if reset='1' then
      failure2 <= '0';
    elsif clk2'event and clk2='1' then
      if failure2='0' then
        if state_reg2=READ then
          if dout2/=rand2_reg_2(dout2'range) then
            failure2 <= '1';
            assert 1=0
            report "Error in port 2."
                    severity failure;
          end if;
        end if;
      end if;
    end if;
  end process;

end arch_ram_test;