ramlib_xil.vhd

该文件时RAM的源文件和测试文件以及仿真文件

                or (block_type=2 and register_out_flag=1) generate
  begin
    RAM_BLOCK0: component ram_dp_block
        generic map (addr_bits, data_bits, register_out_flag, block_type)
        port map (reset, wr_clk, wr_en, wr_addr, wr_data, rd_clk, rd_addr, rd_data);
  end generate RAM_BLOCK;
end arch_ram_dp;


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-- Note:  This entity only works for addr_bits>12
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;

entity ram_x1_dp2_block is
    generic (addr_bits	:integer);
    port (reset		:in  std_logic;
          p1_clk	:in  std_logic;
          p1_we		:in  std_logic;
          p1_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          p1_din	:in  std_logic;
          p1_dout	:out std_logic;
          p2_clk	:in  std_logic;
          p2_we		:in  std_logic;
          p2_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          p2_din	:in  std_logic;
          p2_dout	:out std_logic
         );
end ram_x1_dp2_block;


architecture arch_ram_x1_dp2_block of ram_x1_dp2_block is
  signal p1_rdata 	:std_logic_vector ((2**(addr_bits-12))-1 downto 0);
  signal p2_rdata 	:std_logic_vector ((2**(addr_bits-12))-1 downto 0);
  
  signal p1_we_int	:std_logic_vector ((2**(addr_bits-12))-1 downto 0);
  signal p2_we_int	:std_logic_vector ((2**(addr_bits-12))-1 downto 0);

  signal p1_addr_reg	:std_logic_vector (addr_bits-12-1 downto 0);
  signal p2_addr_reg	:std_logic_vector (addr_bits-12-1 downto 0);
  
  signal p1_wdata	:std_logic_vector (0 downto 0);
  signal p2_wdata	:std_logic_vector (0 downto 0);

  signal always_one	:std_logic;

begin
  always_one <= '1';

  p1_wdata(0) <= p1_din;
  p2_wdata(0) <= p2_din;
  
  ------------------------------------
  -- Array of RAM Blocks
  RAMX1_DP: for i in (2**(addr_bits-12))-1 downto 0 generate
  begin
    RAMX1:  component RAMB4_S1_S1 port map
          (p1_we_int(i), always_one, reset, p1_clk, p1_addr(11 downto 0), p1_wdata, p1_rdata(i downto i),
           p2_we_int(i), always_one, reset, p2_clk, p2_addr(11 downto 0), p2_wdata, p2_rdata(i downto i));
  end generate RAMX1_DP;


  ------------------------------------
  -- Generate the write enables
  WE_GEN0:  for i in (2**(addr_bits-12))-1 downto 0 generate
  begin
    process (p1_addr, p1_we)
    begin
      if integer_to_slv(i, addr_bits-12) = p1_addr(addr_bits-1 downto 12) and p1_we='1' then
        p1_we_int(i) <= '1';
      else
        p1_we_int(i) <= '0';
      end if;
    end process;
  end generate WE_GEN0;

  WE_GEN1:  for i in (2**(addr_bits-12))-1 downto 0 generate
  begin
    process (p2_addr, p2_we)
    begin
      if integer_to_slv(i, addr_bits-12) = p2_addr(addr_bits-1 downto 12) and p2_we='1' then
        p2_we_int(i) <= '1';
      else
        p2_we_int(i) <= '0';
      end if;
    end process;
  end generate WE_GEN1;

  ------------------------------------
  -- Register the upper read address bits
  process (reset, p1_clk)
  begin
    if reset='1' then
      p1_addr_reg <= (others=>'0');
    elsif p1_clk'event and p1_clk='1' then
      p1_addr_reg <= p1_addr (addr_bits-1 downto 12);
    end if;
  end process;

  process (reset, p2_clk)
  begin
    if reset='1' then
      p2_addr_reg <= (others=>'0');
    elsif p2_clk'event and p2_clk='1' then
      p2_addr_reg <= p2_addr (addr_bits-1 downto 12);
    end if;
  end process;

  ------------------------------------
  -- Mux the data outputs
  p1_dout <= p1_rdata(slv_to_integer(p1_addr_reg));
  p2_dout <= p2_rdata(slv_to_integer(p2_addr_reg));

end arch_ram_x1_dp2_block;


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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;

entity ram_dp2 is
    generic (addr_bits		:integer;
             data_bits		:integer;
             block_type		:integer := 0);
    port (reset		:in  std_logic;
          p1_clk	:in  std_logic;
          p1_we		:in  std_logic;
          p1_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          p1_din	:in  std_logic_vector (data_bits-1 downto 0);
          p1_dout	:out std_logic_vector (data_bits-1 downto 0);

          p2_clk	:in  std_logic;
          p2_we		:in  std_logic;
          p2_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          p2_din	:in  std_logic_vector (data_bits-1 downto 0);
          p2_dout	:out std_logic_vector (data_bits-1 downto 0)          
         ); 
end ram_dp2;


architecture arch_ram_dp2 of ram_dp2 is
  signal always_one	:std_logic;
  signal always_zero	:std_logic;

  signal p1_addr_min 	:std_logic_vector (7 downto 0);
  signal p2_addr_min 	:std_logic_vector (7 downto 0);

  signal p1_lastin	:std_logic_vector (15 downto 0);
  signal p2_lastin	:std_logic_vector (15 downto 0);

  signal p1_lastout	:std_logic_vector (15 downto 0);
  signal p2_lastout	:std_logic_vector (15 downto 0);
  
begin
  always_one <= '1';
  always_zero <= '0';

  --------------------------------------------
  -- Needs smaller than a 256xN RAM, use 256x16's anyway
  --------------------------------------------
  ADDRMIN:  if addr_bits<8 generate
  begin
    -- Zero out (and drive) the high address bits
    CLEARMIN_ADDR: for i in p1_addr_min'high downto addr_bits generate
    begin
      p1_addr_min(i) <= '0';
      p2_addr_min(i) <= '0';
    end generate CLEARMIN_ADDR;
    
    p1_addr_min(addr_bits-1 downto 0) <= p1_addr;
    p2_addr_min(addr_bits-1 downto 0) <= p2_addr;

    RAMMIN:  for i in 0 to (data_bits/16)-1 generate
    begin
      RAMX16:  component RAMB4_S16_S16 port map
          (p1_we      , always_one, reset, p1_clk, p1_addr_min, p1_din(16*i+15 downto 16*i),  p1_dout(16*i+15 downto 16*i),
           p2_we      , always_one, reset, p2_clk, p2_addr_min, p2_din(16*i+15 downto 16*i),  p2_dout(16*i+15 downto 16*i) );
    end generate RAMMIN;

    RAMMINA:  if (data_bits mod 16) /= 0 generate
    begin
      CLEARMIN: for i in p1_lastin'high downto (data_bits mod 16) generate
      begin
        p1_lastin(i) <= '0';
        p2_lastin(i) <= '0';
      end generate CLEARMIN;
      
      p1_lastin((data_bits mod 16)-1 downto 0) <= p1_din(data_bits-1 downto data_bits-(data_bits mod 16));
      p2_lastin((data_bits mod 16)-1 downto 0) <= p2_din(data_bits-1 downto data_bits-(data_bits mod 16));

      p1_dout(data_bits-1 downto data_bits-(data_bits mod 16)) <= p1_lastout((data_bits mod 16)-1 downto 0);
      p2_dout(data_bits-1 downto data_bits-(data_bits mod 16)) <= p2_lastout((data_bits mod 16)-1 downto 0);
      
      RAMX16A:  component RAMB4_S16_S16 port map
          (p1_we      , always_one, reset, p1_clk, p1_addr_min, p1_lastin(15 downto 0),  p1_lastout(15 downto 0),
           p2_we      , always_one, reset, p2_clk, p2_addr_min, p2_lastin(15 downto 0),  p2_lastout(15 downto 0) );
    end generate RAMMINA;
  end generate ADDRMIN;

  --------------------------------------------
  -- Use 256x16 RAM's
  --------------------------------------------
  ADDR8:  if addr_bits=8 generate
  begin
    RAM8:  for i in 0 to (data_bits/16)-1 generate
    begin
      RAMX16:  component RAMB4_S16_S16 port map
          (p1_we      , always_one, reset, p1_clk, p1_addr, p1_din(16*i+15 downto 16*i),  p1_dout(16*i+15 downto 16*i),
           p2_we      , always_one, reset, p2_clk, p2_addr, p2_din(16*i+15 downto 16*i),  p2_dout(16*i+15 downto 16*i) );
    end generate RAM8;

    RAM8A:  if (data_bits mod 16) /= 0 generate
    begin
      CLEAR8: for i in p1_lastin'high downto (data_bits mod 16) generate
      begin
        p1_lastin(i) <= '0';
        p2_lastin(i) <= '0';
      end generate CLEAR8;

      p1_lastin((data_bits mod 16)-1 downto 0) <= p1_din(data_bits-1 downto data_bits-(data_bits mod 16));
      p2_lastin((data_bits mod 16)-1 downto 0) <= p2_din(data_bits-1 downto data_bits-(data_bits mod 16));

      p1_dout(data_bits-1 downto data_bits-(data_bits mod 16)) <= p1_lastout((data_bits mod 16)-1 downto 0);
      p2_dout(data_bits-1 downto data_bits-(data_bits mod 16)) <= p2_lastout((data_bits mod 16)-1 downto 0);

      RAMX16A:  component RAMB4_S16_S16 port map
          (p1_we      , always_one, reset, p1_clk, p1_addr, p1_lastin(15 downto 0),  p1_lastout(15 downto 0),
           p2_we      , always_one, reset, p2_clk, p2_addr, p2_lastin(15 downto 0),  p2_lastout(15 downto 0) );
    end generate RAM8A;
  end generate ADDR8;


  --------------------------------------------
  -- Use 512x8 RAM's 
  --------------------------------------------
  ADDR9:  if addr_bits=9 generate
  begin
    RAM9:  for i in 0 to (data_bits/8)-1 generate
    begin     
      RAMX8:  component RAMB4_S8_S8 port map
          (p1_we      , always_one, reset, p1_clk, p1_addr, p1_din(8*i+7 downto 8*i),  p1_dout(8*i+7 downto 8*i),
           p2_we      , always_one, reset, p2_clk, p2_addr, p2_din(8*i+7 downto 8*i),  p2_dout(8*i+7 downto 8*i) );
    end generate RAM9;

    RAM9A:  if (data_bits mod 8) /= 0 generate
    begin
      CLEAR9: for i in p1_lastin'high downto (data_bits mod 8) generate
      begin
        p1_lastin(i) <= '0';
        p2_lastin(i) <= '0';
      end generate CLEAR9;

      p1_lastin((data_bits mod 8)-1 downto 0) <= p1_din(data_bits-1 downto data_bits-(data_bits mod 8));
      p2_lastin((data_bits mod 8)-1 downto 0) <= p2_din(data_bits-1 downto data_bits-(data_bits mod 8));

      p1_dout(data_bits-1 downto data_bits-(data_bits mod 8)) <= p1_lastout((data_bits mod 8)-1 downto 0);
      p2_dout(data_bits-1 downto data_bits-(data_bits mod 8)) <= p2_lastout((data_bits mod 8)-1 downto 0);

      RAMX8A:  component RAMB4_S8_S8 port map
          (p1_we      , always_one, reset, p1_clk, p1_addr, p1_lastin(7 downto 0),  p1_lastout(7 downto 0),
           p2_we      , always_one, reset, p2_clk, p2_addr, p2_lastin(7 downto 0),  p2_lastout(7 downto 0) );
    end generate RAM9A;
  end generate ADDR9;

  --------------------------------------------
  -- Use 1k x 4 RAM's
  --------------------------------------------
  ADDR10:  if addr_bits=10 generate
  begin
    RAM10:  for i in 0 to (data_bits/4)-1 generate
    begin
      RAMX4:  component RAMB4_S4_S4 port map
          (p1_we      , always_one, reset, p1_clk, p1_addr, p1_din(4*i+3 downto 4*i),  p1_dout(4*i+3 downto 4*i),
           p2_we      , always_one, reset, p2_clk, p2_addr, p2_din(4*i+3 downto 4*i),  p2_dout(4*i+3 downto 4*i) );
    end generate RAM10;

    RAM10A:  if (data_bits mod 4) /= 0 generate
    begin
      CLEAR10: for i in p1_lastin'high downto (data_bits mod 4) generate
      begin
        p1_lastin(i) <= '0';
        p2_lastin(i) <= '0';
      end generate CLEAR10;

      p1_lastin((data_bits mod 4)-1 downto 0) <= p1_din(data_bits-1 downto data_bits-(data_bits mod 4));
      p2_lastin((data_bits mod 4)-1 downto 0) <= p2_din(data_bits-1 downto data_bits-(data_bits mod 4));

      p1_dout(data_bits-1 downto data_bits-(data_bits mod 4)) <= p1_lastout((data_bits mod 4)-1 downto 0);
      p2_dout(data_bits-1 downto data_bits-(data_bits mod 4)) <= p2_lastout((data_bits mod 4)-1 downto 0);

      RAMX4A:  component RAMB4_S4_S4 port map
          (p1_we      , always_one, reset, p1_clk, p1_addr, p1_lastin(3 downto 0),  p1_lastout(3 downto 0),
           p2_we      , always_one, reset, p2_clk, p2_addr, p2_lastin(3 downto 0),  p2_lastout(3 downto 0) );
    end generate RAM10A;
  end generate ADDR10;


  --------------------------------------------
  -- Use 2k x 2 RAM's
  --------------------------------------------
  ADDR11:  if addr_bits=11 generate
  begin
    RAM11:  for i in 0 to (data_bits/2)-1 generate
    begin
      RAMX2:  component RAMB4_S2_S2 port map
          (p1_we      , always_one, reset, p1_clk, p1_addr, p1_din(2*i+1 downto 2*i),  p1_dout(2*i+1 downto 2*i),
           p2_we      , always_one, reset, p2_clk, p2_addr, p2_din(2*i+1 downto 2*i),  p2_dout(2*i+1 downto 2*i) );
    end generate RAM11;

    RAM11A:  if (data_bits mod 2) /= 0 generate
    begin
      CLEAR11: for i in p1_lastin'high downto (data_bits mod 2) generate
      begin
        p1_lastin(i) <= '0';
        p2_lastin(i) <= '0';
      end generate CLEAR11;

      p1_lastin((data_bits mod 2)-1 downto 0) <= p1_din(data_bits-1 downto data_bits-(data_bits mod 2));
      p2_lastin((data_bits mod 2)-1 downto 0) <= p2_din(data_bits-1 downto data_bits-(data_bits mod 2));

      p1_dout(data_bits-1 downto data_bits-(data_bits mod 2)) <= p1_lastout((data_bits mod 2)-1 downto 0);
      p2_dout(data_bits-1 downto data_bits-(data_bits mod 2)) <= p2_lastout((data_bits mod 2)-1 downto 0);

      RAMX2A:  component RAMB4_S2_S2 port map
          (p1_we      , always_one, reset, p1_clk, p1_addr, p1_lastin(1 downto 0),  p1_lastout(1 downto 0),
           p2_we      , always_one, reset, p2_clk, p2_addr, p2_lastin(1 downto 0),  p2_lastout(1 downto 0) );
    end generate RAM11A;
  end generate ADDR11;

  --------------------------------------------
  -- Use 4x k 1 RAM's
  --------------------------------------------
  ADDR12:  if addr_bits=12 generate
  begin
    RAM12:  for i in 0 to data_bits-1 generate
    begin
      RAMX1:  component RAMB4_S1_S1 port map
          (p1_we      , always_one, reset, p1_clk, p1_addr, p1_din(i downto i),  p1_dout(i downto i),
           p2_we      , always_one, reset, p2_clk, p2_addr, p2_din(i downto i),  p2_dout(i downto i) );
    end generate RAM12;
  end generate ADDR12;


  --------------------------------------------
  -- Requires larger than a 4K x N RAM, use a 2-D array of 4Kx1's
  --------------------------------------------
  ADDRMAX:  if addr_bits>12 generate
      signal wr_en_col :std_logic_vector ((2**(addr_bits-12))-1 downto 0);
  begin
    RAMMAX:  for i in 0 to data_bits-1 generate
    begin
      RAMXMAXA:  component ram_x1_dp2_block generic map
                    (addr_bits)
                  port map
                    (reset,
                     p1_clk, p1_we, p1_addr, p1_din(i),  p1_dout(i),
                     p2_clk, p2_we, p2_addr, p2_din(i),  p2_dout(i) );
    end generate RAMMAX;
  end generate ADDRMAX;

end arch_ram_dp2;



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