top.vhd

VGA动画显示

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
    Port (clk:in std_logic;
    		rst:in std_logic;
		rxd:in std_logic;
		hs:buffer std_logic;
		vs:buffer std_logic;
		rgb:out std_logic_vector(7 downto 0));
end top;

architecture Behavioral of top is

component uartrec is
    Port (clk:in std_logic;
		rxd:in std_logic;
		RxAv:out std_logic;
		data:out std_logic_vector(7 downto 0));
end component;

component wrlogo is
    Port (clk:in std_logic;
    		rst:in std_logic;
		RxAv:in std_logic;
		din:in std_logic_vector(7 downto 0);
		hloc:in std_logic_vector(9 downto 0);
		vloc:in std_logic_vector(9 downto 0);
		we:out std_logic;
		logo_flag:out std_logic;
		dout:out std_logic_vector(7 downto 0));
end component;

--component wrground is
--	port(clk:in std_logic;
--		RxAv:in std_logic;
--		ramwe:in std_logic;
--		din:in std_logic_vector;
--		hloc:in std_logic_vector(9 downto 0);
--		vloc:in std_logic_vector(9 downto 0);
--		we:out std_logic;
--		dout:out std_logic_vector(7 downto 0));
--end component;

component vga is
    port
	(clk : in std_logic;
	 rst: in std_logic;
	 hs: buffer std_logic;
	 vs: buffer std_logic;	
      hloc: out std_logic_vector(9 downto 0);	
      vloc: out std_logic_vector(9 downto 0));
end component;

signal logo_flag:std_logic;
signal In_data:std_logic_vector(7 downto 0);
signal RxAv:std_logic;
signal weram:std_logic;
signal data_sram:std_logic_vector(7 downto 0);
signal data_srambuf:std_logic_vector(7 downto 0);
signal data_ram:std_logic_vector(7 downto 0);
signal wesram:std_logic;
signal vgaclk:std_logic;
signal hloc:std_logic_vector(9 downto 0);
signal vloc:std_logic_vector(9 downto 0);

signal counter:integer range 0 to 50000000;
begin

u0:uartrec port map
    (clk =>clk,
     rxd =>rxd,
	RxAv =>RxAv,
	data =>In_data);

u1:wrlogo port map
    (clk =>clk,
     rst =>rst,
	RxAv =>RxAv,
	din =>In_data,
	hloc =>hloc,
	vloc =>vloc,
	we =>weram,
	logo_flag =>logo_flag,
	dout =>data_ram);

--u2:wrground port map
--	(clk =>clk,
--	 RxAv =>RxAv,
--	 ramwe =>weram,
--	 din =>In_data,
--	 hloc =>hloc,
--	 vloc =>vloc,
--	 we =>wesram,
--	 dout =>data_sram);

u4:vga port map
    (clk =>clk,
     rst =>rst,
	hs =>hs,
	vs =>vs,
	hloc =>hloc,
	vloc =>vloc);

process(logo_flag)
begin
  if logo_flag='1' then
    data_srambuf<="00000000";
  else
    data_srambuf<=data_sram;
  end if;
end process;

process(wesram,logo_flag)
begin
  if wesram='1' then
    rgb<=data_ram;
  else
      rgb<=data_ram or data_srambuf;
  end if;
end process;

end Behavioral;