top.vhd

i2c接口编程试验

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
	port(sysclk:in std_logic;
		rst:in std_logic;
		sda:inout std_logic;
		scl:inout std_logic);
end top;

architecture Behavioral of top is
signal clk_counter:integer range 0 to 1500;
signal clkbuf:std_logic;
signal rwflag:std_logic;

signal phase_counter:std_logic_vector(1 downto 0);
signal sdaclk:std_logic;
signal sclbuf:std_logic;
signal sclflag:std_logic;
signal rstbuf:std_logic_vector(7 downto 0);
signal databuf:std_logic_vector(7 downto 0);
signal reserve:std_logic_vector(7 downto 0);
signal state_counter:integer range 0 to 20;
signal ini_counter:integer range 0 to 10;

type state is (waitwritecon,writecon,readdata,writedata,idle);
signal present_state:state;

begin
process(sysclk)
begin
  if sysclk'event and sysclk='1' then
    clk_counter<=clk_counter+1;
    if clk_counter>=1249 then
      clk_counter<=0;
	 clkbuf<=not clkbuf;
    end if;
  end if;
end process;

sdaclk<=phase_counter(0);
sclbuf<=phase_counter(1);
scl<=sclbuf or sclflag;

process(clkbuf)
begin
  if clkbuf'event and clkbuf='1' then
    phase_counter<=phase_counter+1;
  end if;
end process;

process(sdaclk)
begin
  if sdaclk'event and sdaclk='0' then
    ini_counter<=ini_counter+1;
	 if ini_counter>=8 then
	   ini_counter<=8;
	 end if;
  end if;
end process;

process(sdaclk)
begin 
  if sdaclk'event and sdaclk='1' then
    if ini_counter=5 then
	   rwflag<='1';
      present_state<=waitwritecon;
    else
      case present_state is
	   when waitwritecon =>
	     if sclbuf='1' then
		  sda<='0';
		  sclflag<='0';
		  databuf<="0100000"&rwflag;
		  state_counter<=0;
		  present_state<=writecon;
		end if;
	   when writecon =>
	     if sclbuf='0' then
		  sda<=databuf(7);
		  databuf<=databuf(6 downto 0)&'0';
		  state_counter<=state_counter+1;
		  if state_counter=8 then
		    sda<='Z';
		  end if;
		end if;
		if state_counter=9 then
		  state_counter<=0;
		  if rwflag='1' then
		    sda<='Z';
		    present_state<=readdata;
		  else
		    databuf(3 downto 0)<=reserve(4)&reserve(7 downto 5);
		    databuf(7 downto 4)<="1111";
		    present_state<=writedata;
		  end if;
		end if;
	   when readdata =>
		if state_counter<=7 then
		  sda<='Z';
		  if sclbuf='1' then
		    state_counter<=state_counter+1;
		    databuf<=databuf(6 downto 0)&sda;
		  end if;
		elsif state_counter=8 then
		  if sclbuf='0' then
		    reserve<=databuf;
		    state_counter<=state_counter+1;
		    sda<='0';
		  end if;
		elsif state_counter=9 then
		  if sclbuf='0' then
		    state_counter<=state_counter+1;
		    sclflag<='1';
		  end if;
		elsif state_counter=10 then
		  state_counter<=0;
		  rwflag<='0';
		  sda<='1';		 --结束标志
		  present_state<=waitwritecon;--waitwritecon;
		end if;
	   when writedata =>
	     if sclbuf='0' then
		  state_counter<=state_counter+1;
		  if state_counter<=7 then
		    sda<=databuf(7);
		    databuf<=databuf(6 downto 0)&databuf(7);
		  elsif state_counter=8 then
		    sda<='Z';
		  elsif state_counter=9 then
		    sda<='0';
		    sclflag<='1';
		  elsif state_counter=10 then
		    sda<='1';
		    state_counter<=0;
		    present_state<=idle;
		  end if;
		end if;
	   when idle =>
		  rwflag<='1';
	     present_state<=waitwritecon;
	 end case;
    end if;
  end if;
end process;
        	              
end Behavioral;