krtlcd.par

12864图形点阵液晶驱动vhdl程序

Release 6.1i Par G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

YUPC::  Fri Jun 11 14:14:41 2004


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 krtlcd_map.ncd
krtlcd.ncd krtlcd.pcf 


Constraints file: krtlcd.pcf

Loading device database for application Par from file "krtlcd_map.ncd".
   "krtlcd" is an NCD, version 2.38, device xc2s300e, package fg456, speed -6
Loading device for application Par from file '2s300e.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.17 2003-11-04.


Resolved that IOB <lcd_dir> must be placed at site E22.
Resolved that IOB <lcd_rst> must be placed at site E21.
Resolved that IOB <lcd_e> must be placed at site L17.
Resolved that IOB <lcd_k> must be placed at site C21.
Resolved that GCLKIOB <sysclk> must be placed at site AB12.
Resolved that IOB <lcd_di> must be placed at site J17.
Resolved that IOB <lcd_lightkey> must be placed at site T21.
Resolved that IOB <lcd_rw> must be placed at site K17.
Resolved that IOB <lcd_data<0>> must be placed at site F21.
Resolved that IOB <lcd_data<1>> must be placed at site F22.
Resolved that IOB <lcd_data<2>> must be placed at site G21.
Resolved that IOB <lcd_data<3>> must be placed at site G22.
Resolved that IOB <lcd_data<4>> must be placed at site H21.
Resolved that IOB <lcd_data<5>> must be placed at site H22.
Resolved that IOB <lcd_data<6>> must be placed at site J21.
Resolved that IOB <lcd_data<7>> must be placed at site J22.
Resolved that IOB <lcd_modekey> must be placed at site T22.
Resolved that IOB <lcd_cs1> must be placed at site D21.
Resolved that IOB <lcd_cs2> must be placed at site D22.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            18 out of 325     5%
      Number of LOCed External IOBs   18 out of 18    100%

   Number of SLICEs                 1071 out of 3072   34%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98b281) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
...........................................................
Phase 5.8 (Checksum:c7ff9b) REAL time: 7 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 7 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 14 secs 

Writing design to file krtlcd.ncd.

Total REAL time to Placer completion: 14 secs 
Total CPU time to Placer completion: 13 secs 


Phase 1: 7645 unrouted;       REAL time: 15 secs 

Phase 2: 7504 unrouted;       REAL time: 36 secs 

Phase 3: 2996 unrouted;       REAL time: 38 secs 

Phase 4: 0 unrouted;       REAL time: 40 secs 

Total REAL time to Router completion: 41 secs 
Total CPU time to Router completion: 39 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      sysclk_BUFGP          |  Global  |   46   |  0.225     |  0.652      |
+----------------------------+----------+--------+------------+-------------+
|U0_clk_250khzbuf_1          |   Local  |   53   |  2.490     |  4.288      |
+----------------------------+----------+--------+------------+-------------+
|  U0_clk_250khzbuf          |   Local  |   44   |  2.162     |  4.119      |
+----------------------------+----------+--------+------------+-------------+
|U0_clk_250khzbuf_3          |   Local  |   42   |  2.755     |  3.789      |
+----------------------------+----------+--------+------------+-------------+
|U0_clk_250khzbuf_2          |   Local  |   42   |  3.698     |  4.493      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 290


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.944
   The MAXIMUM PIN DELAY IS:                               7.686
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   4.791

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 8.00  d >= 8.00
   ---------   ---------   ---------   ---------   ---------   ---------
        1277        2737        2577         908         146           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 43 secs 
Total CPU time to PAR completion: 40 secs 

Peak Memory Usage:  79 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file krtlcd.ncd.


PAR done.