__projnav.log

12864图形点阵液晶驱动vhdl程序

=========================================================================

Synthesizing Unit <lcdkey>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/lcdkey.vhd.
    Found 1-bit register for signal <lightbuf>.
    Found 2-bit up counter for signal <modebuf>.
    Found 16-bit register for signal <shiftlightkey>.
    Found 16-bit register for signal <shiftmodekey>.
    Summary:
	inferred   1 Counter(s).
	inferred  33 D-type flip-flop(s).
Unit <lcdkey> synthesized.


Synthesizing Unit <lcdclk>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/lcdclk.vhd.
    Found 4-bit comparator lessequal for signal <$n0003> created at line 29.
    Found 1-bit register for signal <clk_250khzbuf>.
    Found 1-bit register for signal <clk_50hzbuf>.
    Found 7-bit up counter for signal <counter_250khz>.
    Found 19-bit up counter for signal <counter_50hz>.
    Found 4-bit up counter for signal <counter_ini>.
    Summary:
	inferred   3 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <lcdclk> synthesized.


Synthesizing Unit <krtlcd>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/krtlcd.vhd.
    Found 1024x8-bit ROM for signal <$n0013> created at line 162.
    Found 1024x8-bit ROM for signal <$n0014> created at line 163.
    Found 1024x8-bit ROM for signal <$n0015> created at line 164.
    Found 1024x8-bit ROM for signal <$n0016> created at line 165.
    Using one-hot encoding for signal <present_state>.
    Found 1-bit register for signal <lcd_cs1>.
    Found 1-bit register for signal <lcd_cs2>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0024> created at line 134.
    Found 3-bit adder for signal <$n0031>.
    Found 4-bit adder for signal <$n0041> created at line 136.
    Found 10-bit adder for signal <$n0064> created at line 171.
    Found 10-bit register for signal <addrbuf>.
    Found 4-bit register for signal <counter_ini>.
    Found 3-bit register for signal <counterbuf>.
    Found 8-bit register for signal <dbbuf>.
    Found 1-bit register for signal <ebuf>.
    Found 2-bit register for signal <present_state>.
    Found 3 1-bit 2-to-1 multiplexers.
WARNING:Xst:1306 - Output <lcd_di> is never assigned.
WARNING:Xst:646 - Signal <clk_50hz> is assigned but never used.
    Summary:
	inferred   4 ROM(s).
	inferred  30 D-type flip-flop(s).
	inferred   3 Adder/Subtracter(s).
	inferred   3 Multiplexer(s).
Unit <krtlcd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 4
  1024x8-bit ROM                   : 4
# Registers                        : 43
  1-bit register                   : 38
  4-bit register                   : 1
  8-bit register                   : 1
  10-bit register                  : 1
  2-bit register                   : 1
  3-bit register                   : 1
# Counters                         : 4
  2-bit up counter                 : 1
  4-bit up counter                 : 1
  7-bit up counter                 : 1
  19-bit up counter                : 1
# Multiplexers                     : 4
  2-to-1 multiplexer               : 3
  3-bit 4-to-1 multiplexer         : 1
# Adders/Subtractors               : 3
  3-bit adder                      : 1
  4-bit adder                      : 1
  10-bit adder                     : 1
# Comparators                      : 1
  4-bit comparator lessequal       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "D:/Xilinx/data/librtl.xst" Consulted
WARNING:Xst:1291 - FF/Latch <clk_50hzbuf> is unconnected in block <u0>.

Optimizing unit <krtlcd> ...

Optimizing unit <lcdclk> ...

Optimizing unit <lcdkey> ...

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_17> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_clk_50hzbuf> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_18> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_0> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_1> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_2> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_3> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_4> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_5> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_6> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_7> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_8> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_9> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_10> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_11> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_12> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_13> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_14> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_15> is unconnected in block <krtlcd>.
WARNING:Xst:1291 - FF/Latch <u0_counter_50hz_16> is unconnected in block <krtlcd>.
Loading device for application Xst from file '2v1000.nph' in environment D:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block krtlcd, actual ratio is 18.
FlipFlop present_state_0 has been replicated 2 time(s)
FlipFlop counterbuf_2 has been replicated 1 time(s)
FlipFlop addrbuf_9 has been replicated 3 time(s)
FlipFlop addrbuf_8 has been replicated 2 time(s)
FlipFlop addrbuf_7 has been replicated 6 time(s)
FlipFlop addrbuf_5 has been replicated 18 time(s)
FlipFlop addrbuf_6 has been replicated 9 time(s)
FlipFlop addrbuf_0 has been replicated 36 time(s)
FlipFlop addrbuf_1 has been replicated 39 time(s)
FlipFlop addrbuf_3 has been replicated 40 time(s)
FlipFlop addrbuf_2 has been replicated 41 time(s)
FlipFlop addrbuf_4 has been replicated 28 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v1000fg456-4 

 Number of Slices:                    1011  out of   5120    19%  
 Number of Slice Flip Flops:           302  out of  10240     2%  
 Number of 4 input LUTs:              1044  out of  10240    10%  
 Number of bonded IOBs:                 17  out of    324     5%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
u0_clk_250khzbuf:q                 | NONE                   | 255   |
sysclk                             | BUFGP                  | 47    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.949ns (Maximum Frequency: 111.744MHz)
   Minimum input arrival time before clock: 1.603ns
   Maximum output required time after clock: 7.794ns
   Maximum combinational path delay: No path found

=========================================================================

Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -quiet -dd e:\hy_zhangwang\lcd\krtlcd/_ngo -uc krtlcd.ucf
-p xc2v1000-fg456-4 krtlcd.ngc krtlcd.ngd 

Reading NGO file "E:/hy_zhangwang/lcd/krtlcd/krtlcd.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "krtlcd.ucf" ...
ERROR:NgdBuild:755 - Line 6 in 'krtlcd.ucf': Could not find net(s) 'lcd_di' in
   the design.  To suppress this error use the -aul switch, specify the correct
   net name or remove the constraint.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "krtlcd.ucf".

Writing NGDBUILD log file "krtlcd.bld"...
ERROR: NGDBUILD failed
Reason: 

Completed process "Translate".


Project Navigator Auto-Make Log File
-------------------------------------



Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 48
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/hy_zhangwang/lcd/krtlcd/lcdclk.vhd in Library work.
Architecture behavioral of Entity lcdclk is up to date.
Compiling vhdl file E:/hy_zhangwang/lcd/krtlcd/krtlcd.vhd in Library work.
Architecture behavioral of Entity krtlcd is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <krtlcd> (Architecture <behavioral>).
Entity <krtlcd> analyzed. Unit <krtlcd> generated.

Analyzing Entity <lcdclk> (Architecture <behavioral>).
Entity <lcdclk> analyzed. Unit <lcdclk> generated.

Analyzing Entity <lcdkey> (Architecture <behavioral>).
Entity <lcdkey> analyzed. Unit <lcdkey> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lcdkey>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/lcdkey.vhd.
    Found 1-bit register for signal <lightbuf>.
    Found 2-bit up counter for signal <modebuf>.
    Found 16-bit register for signal <shiftlightkey>.
    Found 16-bit register for signal <shiftmodekey>.
    Summary:
	inferred   1 Counter(s).
	inferred  33 D-type flip-flop(s).
Unit <lcdkey> synthesized.


Synthesizing Unit <lcdclk>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/lcdclk.vhd.
    Found 4-bit comparator lessequal for signal <$n0003> created at line 29.
    Found 1-bit register for signal <clk_250khzbuf>.
    Found 1-bit register for signal <clk_50hzbuf>.
    Found 7-bit up counter for signal <counter_250khz>.
    Found 19-bit up counter for signal <counter_50hz>.
    Found 4-bit up counter for signal <counter_ini>.
    Summary:
	inferred   3 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <lcdclk> synthesized.


Synthesizing Unit <krtlcd>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/krtlcd.vhd.
    Found 1024x8-bit ROM for signal <$n0014> created at line 162.
    Found 1024x8-bit ROM for signal <$n0015> created at line 163.
    Found 1024x8-bit ROM for signal <$n0016> created at line 164.
    Found 1024x8-bit ROM for signal <$n0017> created at line 165.
    Using one-hot encoding for signal <present_state>.
    Found 1-bit register for signal <lcd_di>.
    Found 1-bit register for signal <lcd_cs1>.
    Found 1-bit register for signal <lcd_cs2>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0025> created at line 134.
    Found 3-bit adder for signal <$n0033>.
    Found 4-bit adder for signal <$n0043> created at line 136.
    Found 10-bit adder for signal <$n0066> created at line 171.
    Found 10-bit register for signal <addrbuf>.
    Found 4-bit register for signal <counter_ini>.
    Found 3-bit register for signal <counterbuf>.
    Found 8-bit register for signal <dbbuf>.
    Found 1-bit register for signal <ebuf>.
    Found 2-bit register for signal <present_state>.
    Found 3 1-bit 2-to-1 multiplexers.
WARNING:Xst:646 - Signal <clk_50hz> is assigned but never used.
    Summary:
	inferred   4 ROM(s).
	inferred  31 D-type flip-flop(s).
	inferred   3 Adder/Subtracter(s).
	inferred   3 Multiplexer(s).
Unit <krtlcd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 4
  1024x8-bit ROM                   : 4
# Registers                        : 44
  1-bit register                   : 39
  4-bit register                   : 1
  8-bit register                   : 1
  10-bit register                  : 1
  2-bit register                   : 1
  3-bit register                   : 1
# Counters                         : 4
  2-bit up counter                 : 1
  4-bit up counter                 : 1
  7-bit up counter                 : 1
  19-bit up counter                : 1
# Multiplexers                     : 4
  2-to-1 multiplexer               : 3
  3-bit 4-to-1 multiplexer         : 1
# Adders/Subtractors               : 3
  3-bit adder                      : 1
  4-bit adder                      : 1
  10-bit adder                     : 1
# Comparators                      : 1
  4-bit comparator lessequal       : 1

=========================================================================

=============================================