__projnav.log

12864图形点阵液晶驱动vhdl程序

  1-bit register                   : 33
# Counters                         : 1
  2-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "D:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <lcdkey> ...

Mapping all equations...
Loading device for application Xst from file '2v1000.nph' in environment D:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lcdkey, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v1000fg456-4 

 Number of Slices:                      22  out of   5120     0%  
 Number of Slice Flip Flops:            35  out of  10240     0%  
 Number of 4 input LUTs:                13  out of  10240     0%  
 Number of bonded IOBs:                  5  out of    324     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
sysclk                             | BUFGP                  | 35    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 3.674ns (Maximum Frequency: 272.183MHz)
   Minimum input arrival time before clock: 1.603ns
   Maximum output required time after clock: 7.656ns
   Maximum combinational path delay: No path found

=========================================================================

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 48
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/KRTLCD is now defined in a different file: was C:/Xilinx/HLDexamples/krtlcd/krtlcd.vhd, now is E:/hy_zhangwang/lcd/krtlcd/krtlcd.vhd
WARNING:HDLParsers:3215 - Unit work/KRTLCD/BEHAVIORAL is now defined in a different file: was C:/Xilinx/HLDexamples/krtlcd/krtlcd.vhd, now is E:/hy_zhangwang/lcd/krtlcd/krtlcd.vhd
WARNING:HDLParsers:3215 - Unit work/LCDCLK is now defined in a different file: was C:/Xilinx/HLDexamples/krtlcd/lcdclk.vhd, now is E:/hy_zhangwang/lcd/krtlcd/lcdclk.vhd
WARNING:HDLParsers:3215 - Unit work/LCDCLK/BEHAVIORAL is now defined in a different file: was C:/Xilinx/HLDexamples/krtlcd/lcdclk.vhd, now is E:/hy_zhangwang/lcd/krtlcd/lcdclk.vhd
Compiling vhdl file E:/hy_zhangwang/lcd/krtlcd/lcdclk.vhd in Library work.
Architecture behavioral of Entity lcdclk is up to date.
Compiling vhdl file E:/hy_zhangwang/lcd/krtlcd/krtlcd.vhd in Library work.
Architecture behavioral of Entity krtlcd is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <krtlcd> (Architecture <behavioral>).
Entity <krtlcd> analyzed. Unit <krtlcd> generated.

Analyzing Entity <lcdclk> (Architecture <behavioral>).
Entity <lcdclk> analyzed. Unit <lcdclk> generated.

Analyzing Entity <lcdkey> (Architecture <behavioral>).
Entity <lcdkey> analyzed. Unit <lcdkey> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lcdkey>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/lcdkey.vhd.
    Found 1-bit register for signal <lightbuf>.
    Found 2-bit up counter for signal <modebuf>.
    Found 16-bit register for signal <shiftlightkey>.
    Found 16-bit register for signal <shiftmodekey>.
    Summary:
	inferred   1 Counter(s).
	inferred  33 D-type flip-flop(s).
Unit <lcdkey> synthesized.


Synthesizing Unit <lcdclk>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/lcdclk.vhd.
    Found 4-bit comparator lessequal for signal <$n0003> created at line 29.
    Found 1-bit register for signal <clk_250khzbuf>.
    Found 1-bit register for signal <clk_50hzbuf>.
    Found 7-bit up counter for signal <counter_250khz>.
    Found 19-bit up counter for signal <counter_50hz>.
    Found 4-bit up counter for signal <counter_ini>.
    Summary:
	inferred   3 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <lcdclk> synthesized.


Synthesizing Unit <krtlcd>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/krtlcd.vhd.
WARNING:Xst:1306 - Output <lcd_di> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<7>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<6>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<5>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<4>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<3>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<2>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<1>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<0>> is never assigned.
WARNING:Xst:1306 - Output <lcd_e> is never assigned.
WARNING:Xst:1306 - Output <lcd_k> is never assigned.
WARNING:Xst:1306 - Output <lcd_rw> is never assigned.
WARNING:Xst:1306 - Output <lcd_cs1> is never assigned.
WARNING:Xst:1306 - Output <lcd_cs2> is never assigned.
WARNING:Xst:1306 - Output <lcd_dir> is never assigned.
WARNING:Xst:1306 - Output <lcd_rst> is never assigned.
WARNING:Xst:646 - Signal <lightbuf> is assigned but never used.
WARNING:Xst:646 - Signal <clk_50hz> is assigned but never used.
WARNING:Xst:646 - Signal <modebuf<1>> is assigned but never used.
WARNING:Xst:646 - Signal <modebuf<0>> is assigned but never used.
WARNING:Xst:646 - Signal <clk_250khz> is assigned but never used.
Unit <krtlcd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 35
  1-bit register                   : 35
# Counters                         : 4
  2-bit up counter                 : 1
  4-bit up counter                 : 1
  7-bit up counter                 : 1
  19-bit up counter                : 1
# Comparators                      : 1
  4-bit comparator lessequal       : 1

=========================================================================

WARNING:Xst:524 - All outputs of the instance <u0> of the block <lcdclk> are unconnected in block <krtlcd>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <u1> of the block <lcdkey> are unconnected in block <krtlcd>.
   This instance will be removed from the design along with all underlying logic
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "D:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <krtlcd> ...

Optimizing unit <lcdclk> ...

Optimizing unit <lcdkey> ...

Mapping all equations...
Loading device for application Xst from file '2v1000.nph' in environment D:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block krtlcd, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v1000fg456-4 



=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 48
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/hy_zhangwang/lcd/krtlcd/lcdclk.vhd in Library work.
Architecture behavioral of Entity lcdclk is up to date.
Compiling vhdl file E:/hy_zhangwang/lcd/krtlcd/krtlcd.vhd in Library work.
ERROR:HDLParsers:3312 - E:/hy_zhangwang/lcd/krtlcd/krtlcd.vhd Line 50. Undefined symbol 'lcdkey'.
--> 

Total memory usage is 44164 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------



Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 48
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/hy_zhangwang/lcd/krtlcd/lcdclk.vhd in Library work.
Architecture behavioral of Entity lcdclk is up to date.
Compiling vhdl file E:/hy_zhangwang/lcd/krtlcd/krtlcd.vhd in Library work.
Architecture behavioral of Entity krtlcd is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <krtlcd> (Architecture <behavioral>).
Entity <krtlcd> analyzed. Unit <krtlcd> generated.

Analyzing Entity <lcdclk> (Architecture <behavioral>).
Entity <lcdclk> analyzed. Unit <lcdclk> generated.

Analyzing Entity <lcdkey> (Architecture <behavioral>).
Entity <lcdkey> analyzed. Unit <lcdkey> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lcdkey>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/lcdkey.vhd.
    Found 1-bit register for signal <lightbuf>.
    Found 2-bit up counter for signal <modebuf>.
    Found 16-bit register for signal <shiftlightkey>.
    Found 16-bit register for signal <shiftmodekey>.
    Summary:
	inferred   1 Counter(s).
	inferred  33 D-type flip-flop(s).
Unit <lcdkey> synthesized.


Synthesizing Unit <lcdclk>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/lcdclk.vhd.
    Found 4-bit comparator lessequal for signal <$n0003> created at line 29.
    Found 1-bit register for signal <clk_250khzbuf>.
    Found 1-bit register for signal <clk_50hzbuf>.
    Found 7-bit up counter for signal <counter_250khz>.
    Found 19-bit up counter for signal <counter_50hz>.
    Found 4-bit up counter for signal <counter_ini>.
    Summary:
	inferred   3 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <lcdclk> synthesized.


Synthesizing Unit <krtlcd>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/krtlcd.vhd.
WARNING:Xst:1306 - Output <lcd_di> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<7>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<6>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<5>> is never assigned.