__projnav.log

12864图形点阵液晶驱动vhdl程序

Scanning    lcdclk.vhd
Scanning    lcdclk.vhd
Writing lcdclk.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



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JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    lcdclk.vhd
Scanning    lcdclk.vhd
Writing lcdclk.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    lcdclk.vhd
Scanning    lcdclk.vhd
Writing lcdclk.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
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JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    lcdkey.vhd
Scanning    lcdkey.vhd
Writing lcdkey.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    lcdkey.vhd
Scanning    lcdkey.vhd
Writing lcdkey.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/Xilinx/HLDexamples/krtlcd/lcdclk.vhd in Library work.
Entity <lcdclk> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/Xilinx/HLDexamples/krtlcd/krtlcd.vhd in Library work.
Entity <krtlcd> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <krtlcd> (Architecture <behavioral>).
Entity <krtlcd> analyzed. Unit <krtlcd> generated.

Analyzing Entity <lcdclk> (Architecture <behavioral>).
Entity <lcdclk> analyzed. Unit <lcdclk> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lcdclk>.
    Related source file is C:/Xilinx/HLDexamples/krtlcd/lcdclk.vhd.
    Found 4-bit comparator lessequal for signal <$n0003> created at line 29.
    Found 1-bit register for signal <clk_250khzbuf>.
    Found 1-bit register for signal <clk_50hzbuf>.
    Found 7-bit up counter for signal <counter_250khz>.
    Found 19-bit up counter for signal <counter_50hz>.
    Found 4-bit up counter for signal <counter_ini>.
    Summary:
	inferred   3 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <lcdclk> synthesized.


Synthesizing Unit <krtlcd>.
    Related source file is C:/Xilinx/HLDexamples/krtlcd/krtlcd.vhd.
WARNING:Xst:1306 - Output <lcd_di> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<7>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<6>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<5>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<4>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<3>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<2>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<1>> is never assigned.
WARNING:Xst:1306 - Output <lcd_data<0>> is never assigned.
WARNING:Xst:1306 - Output <lcd_e> is never assigned.
WARNING:Xst:1306 - Output <lcd_k> is never assigned.
WARNING:Xst:1306 - Output <lcd_rw> is never assigned.
WARNING:Xst:1306 - Output <lcd_cs1> is never assigned.
WARNING:Xst:1306 - Output <lcd_cs2> is never assigned.
WARNING:Xst:1306 - Output <lcd_dir> is never assigned.
WARNING:Xst:647 - Input <lcd_modekey> is never used.
WARNING:Xst:1306 - Output <lcd_rst> is never assigned.
WARNING:Xst:647 - Input <lcd_lightkey> is never used.
WARNING:Xst:646 - Signal <clk_50hz> is assigned but never used.
WARNING:Xst:646 - Signal <clk_250khz> is assigned but never used.
Unit <krtlcd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
  1-bit register                   : 2
# Counters                         : 3
  4-bit up counter                 : 1
  7-bit up counter                 : 1
  19-bit up counter                : 1
# Comparators                      : 1
  4-bit comparator lessequal       : 1

=========================================================================

WARNING:Xst:524 - All outputs of the instance <u0> of the block <lcdclk> are unconnected in block <krtlcd>.
   This instance will be removed from the design along with all underlying logic
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <krtlcd> ...

Optimizing unit <lcdclk> ...

Mapping all equations...
Loading device for application Xst from file '2v1000.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block krtlcd, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v1000fg456-4 



=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================

Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -quiet -dd c:\xilinx\hldexamples\krtlcd/_ngo -uc
krtlcd.ucf -p xc2v1000-fg456-4 krtlcd.ngc krtlcd.ngd 

Reading NGO file "C:/Xilinx/HLDexamples/krtlcd/krtlcd.ngc" ...
Reading component libraries for design expansion...
Loading design module "C:\Xilinx\HLDexamples\krtlcd/krtlcd.ngc"...
FATAL_ERROR:NgdBuild:basnbmain.c:1910:1.71.4.1 - Design is empty.   Process will
   terminate.  To resolve this error, please consult the Answers Database and
   other online resources at http://support.xilinx.com. If you need further
   assistance, please open a Webcase by clicking on the "WebCase" link at
   http://support.xilinx.com
ERROR: NGDBUILD failed
Reason: 

Completed process "Translate".



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Started process "Translate".


Command Line: ngdbuild -quiet -dd e:\hy_zhangwang\lcd\krtlcd/_ngo -uc krtlcd.ucf
-p xc2v1000-fg456-4 krtlcd.ngc krtlcd.ngd 

Reading NGO file "E:/hy_zhangwang/lcd/krtlcd/krtlcd.ngc" ...
Reading component libraries for design expansion...
Loading design module "E:\hy_zhangwang\lcd\krtlcd/krtlcd.ngc"...
FATAL_ERROR:NgdBuild:basnbmain.c:1910:1.71.4.1 - Design is empty.   Process will
   terminate.  To resolve this error, please consult the Answers Database and
   other online resources at http://support.xilinx.com. If you need further
   assistance, please open a Webcase by clicking on the "WebCase" link at
   http://support.xilinx.com
ERROR: NGDBUILD failed
Reason: 

Completed process "Translate".


Project Navigator Auto-Make Log File
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Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 48
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file E:\hy_zhangwang\lcd\krtlcd/lcdkey.vhd, automatic determination of correct order of compilation of files in project file lcdkey.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file E:\hy_zhangwang\lcd\krtlcd/lcdkey.vhd in Library work.
ERROR:HDLParsers:164 - E:\hy_zhangwang\lcd\krtlcd/lcdkey.vhd Line 39. parse error, unexpected PROCESS, expecting IF
ERROR:HDLParsers:164 - E:\hy_zhangwang\lcd\krtlcd/lcdkey.vhd Line 44. parse error, unexpected IDENTIFIER, expecting IF
--> 

Total memory usage is 44164 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 48
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/hy_zhangwang/lcd/krtlcd/lcdkey.vhd in Library work.
Entity <lcdkey> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <lcdkey> (Architecture <behavioral>).
Entity <lcdkey> analyzed. Unit <lcdkey> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lcdkey>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/lcdkey.vhd.
    Found 1-bit register for signal <lightbuf>.
    Found 2-bit up counter for signal <modebuf>.
    Found 16-bit register for signal <shiftlightkey>.
    Found 16-bit register for signal <shiftmodekey>.
    Summary:
	inferred   1 Counter(s).
	inferred  33 D-type flip-flop(s).
Unit <lcdkey> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 33