__projnav.log

12864图形点阵液晶驱动vhdl程序

Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    krtlcd.vhd
Scanning    krtlcd.vhd
Writing krtlcd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    krtlcd.vhd
Scanning    krtlcd.vhd
Writing krtlcd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    lcdclk.vhd
Scanning    lcdclk.vhd
Writing lcdclk.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    krtlcd.vhd
Scanning    krtlcd.vhd
Writing krtlcd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    lcdclk.vhd
Scanning    lcdclk.vhd
Writing lcdclk.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file
   C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd, automatic determination of correct
   order of compilation of files in project file vhdtdtfi.prj is not possible.
   Please compile your vhdl file(s) individually to find and fix the error(s) in
   your vhdl file(s). Defaulting to compilation in the order vhdl file names
   appear in the project file.
Compiling vhdl file C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd in Library work.
ERROR:HDLParsers:1411 - C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd Line 36.
   Parameter clk_250khz of mode out can not be associated with a formal
   parameter of mode in.
ERROR:HDLParsers:1411 - C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd Line 43.
   Parameter clk_50hz of mode out can not be associated with a formal parameter
   of mode in.
ERROR:HDLParsers:164 - C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd Line 49. parse
   error, unexpected PROCESS, expecting IF
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    t_lcdclk.vhd
Scanning    t_lcdclk.vhd
Writing t_lcdclk.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    t_lcdclk.vhd
Scanning    t_lcdclk.vhd
Writing t_lcdclk.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd, automatic determination of correct order of compilation of files in project file lcdclk.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd in Library work.
ERROR:HDLParsers:1411 - C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd Line 36. Parameter clk_250khz of mode out can not be associated with a formal parameter of mode in.
ERROR:HDLParsers:1411 - C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd Line 43. Parameter clk_50hz of mode out can not be associated with a formal parameter of mode in.
ERROR:HDLParsers:164 - C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd Line 49. parse error, unexpected PROCESS, expecting IF
--> 

Total memory usage is 42432 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    lcdclk.vhd
Scanning    lcdclk.vhd
Writing lcdclk.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd, automatic determination of correct order of compilation of files in project file lcdclk.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd in Library work.
ERROR:HDLParsers:164 - C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd Line 49. parse error, unexpected PROCESS, expecting IF
ERROR:HDLParsers:164 - C:\Xilinx\HLDexamples\krtlcd/lcdclk.vhd Line 54. parse error, unexpected IDENTIFIER, expecting IF
--> 

Total memory usage is 42432 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    lcdclk.vhd
Scanning    lcdclk.vhd
Writing lcdclk.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/Xilinx/HLDexamples/krtlcd/lcdclk.vhd in Library work.
Entity <lcdclk> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <lcdclk> (Architecture <behavioral>).
Entity <lcdclk> analyzed. Unit <lcdclk> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lcdclk>.
    Related source file is C:/Xilinx/HLDexamples/krtlcd/lcdclk.vhd.
    Found 4-bit comparator lessequal for signal <$n0003> created at line 29.
    Found 1-bit register for signal <clk_250khzbuf>.
    Found 1-bit register for signal <clk_50hzbuf>.
    Found 8-bit up counter for signal <counter_250khz>.
    Found 20-bit up counter for signal <counter_50hz>.
    Found 4-bit up counter for signal <counter_ini>.
    Summary:
	inferred   3 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <lcdclk> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
  1-bit register                   : 2
# Counters                         : 3
  4-bit up counter                 : 1
  8-bit up counter                 : 1
  20-bit up counter                : 1
# Comparators                      : 1
  4-bit comparator lessequal       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <lcdclk> ...

Mapping all equations...
Loading device for application Xst from file '2v1000.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lcdclk, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v1000fg456-4 

 Number of Slices:                      26  out of   5120     0%  
 Number of Slice Flip Flops:            34  out of  10240     0%  
 Number of 4 input LUTs:                49  out of  10240     0%  
 Number of bonded IOBs:                  2  out of    324     0%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
sysclk                             | BUFGP                  | 34    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 6.856ns (Maximum Frequency: 145.858MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.465ns
   Maximum combinational path delay: No path found

=========================================================================

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    lcdclk.vhd
Scanning    lcdclk.vhd
Writing lcdclk.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.