krtlcd.syr

12864图形点阵液晶驱动vhdl程序

#      1-bit register              : 39
#      10-bit register             : 1
#      19-bit register             : 5
#      3-bit register              : 1
#      4-bit register              : 1
#      8-bit register              : 1
# Adders/Subtractors               : 7
#      10-bit adder                : 1
#      19-bit adder                : 5
#      4-bit adder                 : 1
# Comparators                      : 2
#      29-bit comparator greatequal: 1
#      4-bit comparator lessequal  : 1

Cell Usage :
# BELS                             : 2742
#      GND                         : 1
#      LUT1                        : 61
#      LUT1_D                      : 1
#      LUT1_L                      : 33
#      LUT2                        : 16
#      LUT2_D                      : 2
#      LUT2_L                      : 58
#      LUT3                        : 61
#      LUT3_D                      : 2
#      LUT3_L                      : 200
#      LUT4                        : 200
#      LUT4_D                      : 19
#      LUT4_L                      : 932
#      MUXCY                       : 77
#      MUXF5                       : 691
#      MUXF6                       : 338
#      VCC                         : 1
#      XORCY                       : 49
# FlipFlops/Latches                : 387
#      FD                          : 32
#      FD_1                        : 292
#      FDE                         : 3
#      FDR                         : 32
#      FDRE                        : 7
#      FDS                         : 2
#      FDS_1                       : 15
#      FDSE                        : 4
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 18
#      IBUF                        : 2
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300efg456-6 

 Number of Slices:                    1037  out of   3072    33%  
 Number of Slice Flip Flops:           387  out of   6144     6%  
 Number of 4 input LUTs:              1585  out of   6144    25%  
 Number of bonded IOBs:                 18  out of    329     5%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
U0_clk_250khzbuf_1:Q               | NONE                   | 77    |
U0_clk_250khzbuf:Q                 | NONE                   | 77    |
U0_clk_250khzbuf_3:Q               | NONE                   | 77    |
U0_clk_250khzbuf_2:Q               | NONE                   | 77    |
sysclk                             | BUFGP                  | 79    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 12.132ns (Maximum Frequency: 82.427MHz)
   Minimum input arrival time before clock: 2.441ns
   Maximum output required time after clock: 6.914ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U0_clk_250khzbuf_1:Q'
Delay:               12.132ns (Levels of Logic = 7)
  Source:            addrbuf_4_33 (FF)
  Destination:       dbbuf_2 (FF)
  Source Clock:      U0_clk_250khzbuf_1:Q falling
  Destination Clock: U0_clk_250khzbuf_1:Q falling

  Data Path: addrbuf_4_33 to dbbuf_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD_1:C->Q            20   0.992   3.000  addrbuf_4_33 (addrbuf_4_33)
     LUT4:I2->O            1   0.468   0.920  Mrom__n0016_inst_mux_f6_248_SW0 (N53782)
     LUT4:I3->O            1   0.468   0.920  Mrom__n0016_inst_mux_f6_248 (Mrom__n0016__net1170)
     LUT4:I2->O            1   0.468   0.000  Mrom__n0016_inst_lut4_7911 (Mrom__n0016__net1179)
     MUXF6:I0->O           1   0.220   0.920  Mrom__n0016_inst_mux_f6_253 (Mrom__n0016__net1195)
     LUT4:I2->O            1   0.468   0.000  _n0031<2>331_G (N55238)
     MUXF5:I1->O           1   0.403   0.920  _n0031<2>331 (CHOICE2777)
     LUT4:I2->O            1   0.468   0.920  _n0031<2>109 (CHOICE2786)
     FDS_1:S                   0.577          dbbuf_2
    ----------------------------------------
    Total                     12.132ns (4.532ns logic, 7.600ns route)
                                       (37.4% logic, 62.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U0_clk_250khzbuf:Q'
Delay:               8.085ns (Levels of Logic = 4)
  Source:            addrbuf_0_4 (FF)
  Destination:       addrbuf_1 (FF)
  Source Clock:      U0_clk_250khzbuf:Q falling
  Destination Clock: U0_clk_250khzbuf:Q falling

  Data Path: addrbuf_0_4 to addrbuf_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD_1:C->Q            19   0.992   2.950  addrbuf_0_4 (addrbuf_0_4)
     LUT1_D:I0->LO         1   0.468   0.000  Madd__n0046_inst_lut2_01 (N55286)
     MUXCY:S->O            1   0.515   0.000  Madd__n0046_inst_cy_0 (Madd__n0046_inst_cy_0)
     XORCY:CI->O           3   0.648   1.320  Madd__n0046_inst_sum_1 (_n0046<1>)
     LUT4_D:I2->LO         1   0.468   0.000  _n0033<1>1 (N55259)
     FD_1:D                    0.724          addrbuf_1
    ----------------------------------------
    Total                      8.085ns (3.815ns logic, 4.270ns route)
                                       (47.2% logic, 52.8% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U0_clk_250khzbuf_3:Q'
Delay:               7.369ns (Levels of Logic = 3)
  Source:            addrbuf_2_1 (FF)
  Destination:       addrbuf_2 (FF)
  Source Clock:      U0_clk_250khzbuf_3:Q falling
  Destination Clock: U0_clk_250khzbuf_3:Q falling

  Data Path: addrbuf_2_1 to addrbuf_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD_1:C->Q            21   0.992   3.025  addrbuf_2_1 (addrbuf_2_1)
     LUT1:I0->O            1   0.468   0.000  addrbuf<2>_rt (addrbuf<2>_rt)
     XORCY:LI->O           3   0.372   1.320  Madd__n0046_inst_sum_2 (_n0046<2>)
     LUT4_D:I2->LO         1   0.468   0.000  _n0033<2>1_1 (N56509)
     FD_1:D                    0.724          addrbuf_2_5
    ----------------------------------------
    Total                      7.369ns (3.024ns logic, 4.345ns route)
                                       (41.0% logic, 59.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U0_clk_250khzbuf_2:Q'
Delay:               7.990ns (Levels of Logic = 4)
  Source:            addrbuf_3_1 (FF)
  Destination:       addrbuf_4 (FF)
  Source Clock:      U0_clk_250khzbuf_2:Q falling
  Destination Clock: U0_clk_250khzbuf_2:Q falling

  Data Path: addrbuf_3_1 to addrbuf_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD_1:C->Q            21   0.992   3.025  addrbuf_3_1 (addrbuf_3_1)
     LUT1:I0->O            1   0.468   0.000  addrbuf<3>_rt (addrbuf<3>_rt)
     MUXCY:S->O            1   0.515   0.000  Madd__n0046_inst_cy_3 (Madd__n0046_inst_cy_3)
     XORCY:CI->O           2   0.648   1.150  Madd__n0046_inst_sum_4 (_n0046<4>)
     LUT4_D:I2->LO         1   0.468   0.000  _n0033<4>1 (N55265)
     FD_1:D                    0.724          addrbuf_4
    ----------------------------------------
    Total                      7.990ns (3.815ns logic, 4.175ns route)
                                       (47.7% logic, 52.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'sysclk'
Delay:               10.281ns (Levels of Logic = 30)
  Source:            U1_counter_7 (FF)
  Destination:       U1_counter_27 (FF)
  Source Clock:      sysclk rising
  Destination Clock: sysclk rising

  Data Path: U1_counter_7 to U1_counter_27
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.992   1.320  U1_counter_7 (U1_counter_7)
     LUT1_L:I0->LO         1   0.468   0.000  U1_counter<7>_rt1 (U1_counter<7>_rt1)
     MUXCY:S->O            1   0.515   0.000  U1_Mcompar__n0007_inst_cy_69 (U1_Mcompar__n0007_inst_cy_69)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_70 (U1_Mcompar__n0007_inst_cy_70)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_71 (U1_Mcompar__n0007_inst_cy_71)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_72 (U1_Mcompar__n0007_inst_cy_72)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_73 (U1_Mcompar__n0007_inst_cy_73)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_74 (U1_Mcompar__n0007_inst_cy_74)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_75 (U1_Mcompar__n0007_inst_cy_75)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_76 (U1_Mcompar__n0007_inst_cy_76)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_77 (U1_Mcompar__n0007_inst_cy_77)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_78 (U1_Mcompar__n0007_inst_cy_78)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_79 (U1_Mcompar__n0007_inst_cy_79)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_80 (U1_Mcompar__n0007_inst_cy_80)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_81 (U1_Mcompar__n0007_inst_cy_81)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_82 (U1_Mcompar__n0007_inst_cy_82)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_83 (U1_Mcompar__n0007_inst_cy_83)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_84 (U1_Mcompar__n0007_inst_cy_84)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_85 (U1_Mcompar__n0007_inst_cy_85)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_86 (U1_Mcompar__n0007_inst_cy_86)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_87 (U1_Mcompar__n0007_inst_cy_87)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_88 (U1_Mcompar__n0007_inst_cy_88)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_89 (U1_Mcompar__n0007_inst_cy_89)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_90 (U1_Mcompar__n0007_inst_cy_90)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_91 (U1_Mcompar__n0007_inst_cy_91)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_92 (U1_Mcompar__n0007_inst_cy_92)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_93 (U1_Mcompar__n0007_inst_cy_93)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_94 (U1_Mcompar__n0007_inst_cy_94)
     MUXCY:CI->O           1   0.058   0.000  U1_Mcompar__n0007_inst_cy_95 (U1_Mcompar__n0007_inst_cy_95)
     MUXCY:CI->O           2   0.058   1.150  U1_Mcompar__n0007_inst_cy_96 (U1__n0007)
     LUT4:I0->O           29   0.468   3.225  U1__n00021 (U1__n0002)
     FDR:R                     0.577          U1_counter_0
    ----------------------------------------
    Total                     10.281ns (4.586ns logic, 5.695ns route)
                                       (44.6% logic, 55.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'sysclk'
Offset:              2.441ns (Levels of Logic = 1)
  Source:            lcd_lightkey (PAD)
  Destination:       U1_shiftlightkey_15 (FF)
  Destination Clock: sysclk rising

  Data Path: lcd_lightkey to U1_shiftlightkey_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.797   0.920  lcd_lightkey_IBUF (lcd_lightkey_IBUF)
     FD:D                      0.724          U1_shiftlightkey_15
    ----------------------------------------
    Total                      2.441ns (1.521ns logic, 0.920ns route)
                                       (62.3% logic, 37.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'U0_clk_250khzbuf_1:Q'
Offset:              6.914ns (Levels of Logic = 1)
  Source:            ebuf (FF)
  Destination:       lcd_e (PAD)
  Source Clock:      U0_clk_250khzbuf_1:Q falling

  Data Path: ebuf to lcd_e
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS_1:C->Q            3   0.992   1.320  ebuf (ebuf)
     OBUF:I->O                 4.602          lcd_e_OBUF (lcd_e)
    ----------------------------------------
    Total                      6.914ns (5.594ns logic, 1.320ns route)
                                       (80.9% logic, 19.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'sysclk'
Offset:              6.744ns (Levels of Logic = 1)
  Source:            U1_lightbuf (FF)
  Destination:       lcd_k (PAD)
  Source Clock:      sysclk rising

  Data Path: U1_lightbuf to lcd_k
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.992   1.150  U1_lightbuf (U1_lightbuf)
     OBUF:I->O                 4.602          lcd_k_OBUF (lcd_k)
    ----------------------------------------
    Total                      6.744ns (5.594ns logic, 1.150ns route)
                                       (82.9% logic, 17.1% route)

=========================================================================
CPU : 83.75 / 84.58 s | Elapsed : 83.00 / 84.00 s
 
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Total memory usage is 98864 kilobytes