lcdkey.syr

12864图形点阵液晶驱动vhdl程序

Release 5.2.03i - xst F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.61 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.61 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: lcdkey.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : lcdkey.prj
Input Format                       : VHDL
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : lcdkey
Output Format                      : NGC
Target Device                      : xc2v1000-4fg456

---- Source Options
Entity Name                        : lcdkey
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : lower
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/hy_zhangwang/lcd/krtlcd/lcdkey.vhd in Library work.
Entity <lcdkey> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <lcdkey> (Architecture <behavioral>).
Entity <lcdkey> analyzed. Unit <lcdkey> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lcdkey>.
    Related source file is E:/hy_zhangwang/lcd/krtlcd/lcdkey.vhd.
    Found 1-bit register for signal <lightbuf>.
    Found 2-bit up counter for signal <modebuf>.
    Found 16-bit register for signal <shiftlightkey>.
    Found 16-bit register for signal <shiftmodekey>.
    Summary:
	inferred   1 Counter(s).
	inferred  33 D-type flip-flop(s).
Unit <lcdkey> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 33
  1-bit register                   : 33
# Counters                         : 1
  2-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "D:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <lcdkey> ...

Mapping all equations...
Loading device for application Xst from file '2v1000.nph' in environment D:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lcdkey, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : lcdkey.ngr
Top Level Output File Name         : lcdkey
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 6

Macro Statistics :
# Registers                        : 34
#      1-bit register              : 33
#      2-bit register              : 1

Cell Usage :
# BELS                             : 13
#      LUT1                        : 2
#      LUT2                        : 1
#      LUT4                        : 8
#      LUT4_L                      : 2
# FlipFlops/Latches                : 35
#      FD                          : 32
#      FDE                         : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 5
#      IBUF                        : 2
#      OBUF                        : 3
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v1000fg456-4 

 Number of Slices:                      22  out of   5120     0%  
 Number of Slice Flip Flops:            35  out of  10240     0%  
 Number of 4 input LUTs:                13  out of  10240     0%  
 Number of bonded IOBs:                  5  out of    324     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
sysclk                             | BUFGP                  | 35    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 3.674ns (Maximum Frequency: 272.183MHz)
   Minimum input arrival time before clock: 1.603ns
   Maximum output required time after clock: 7.656ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'sysclk'
Delay:               3.674ns (Levels of Logic = 2)
  Source:            shiftmodekey_4
  Destination:       modebuf_0
  Source Clock:      sysclk rising
  Destination Clock: sysclk rising

  Data Path: shiftmodekey_4 to modebuf_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:c->q               2   0.568   0.790  shiftmodekey_4 (shiftmodekey_4)
     LUT4:i0->o            1   0.439   0.408  _n000224 (choice132)
     LUT4:i1->o            2   0.439   0.790  _n000275 (_n0002)
     FDE:ce                    0.240          modebuf_0
    ----------------------------------------
    Total                      3.674ns (1.686ns logic, 1.988ns route)
                                       (45.9% logic, 54.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'sysclk'
Offset:              1.603ns (Levels of Logic = 1)
  Source:            lcd_modekey
  Destination:       shiftmodekey_15
  Destination Clock: sysclk rising

  Data Path: lcd_modekey to shiftmodekey_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:i->o             1   0.825   0.408  lcd_modekey_ibuf (lcd_modekey_ibuf)
     FD:d                      0.370          shiftmodekey_15
    ----------------------------------------
    Total                      1.603ns (1.195ns logic, 0.408ns route)
                                       (74.5% logic, 25.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'sysclk'
Offset:              7.656ns (Levels of Logic = 1)
  Source:            modebuf_0
  Destination:       lcd_modebuf<0>
  Source Clock:      sysclk rising

  Data Path: modebuf_0 to lcd_modebuf<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:c->q              3   0.568   0.981  modebuf_0 (modebuf_0)
     OBUF:i->o                 6.107          lcd_modebuf_0_obuf (lcd_modebuf<0>)
    ----------------------------------------
    Total                      7.656ns (6.675ns logic, 0.981ns route)
                                       (87.2% logic, 12.8% route)

=========================================================================
CPU : 7.00 / 8.04 s | Elapsed : 7.00 / 8.00 s
 
--> 

Total memory usage is 73308 kilobytes