fp.vhd

一个使用VHDL编写的音乐芯片的程序有很好的使用价值

library ieee;
use ieee.std_logic_1164.all;
entity fp is
port(clk:in std_logic;
     cp:out std_logic );
end fp;
architecture des of fp is
signal a:std_logic;
begin
process(clk)
variable n:integer range 0 to 9999;
begin
if clk'event and clk='1' then
  if n<9999 then
  n:=n+1;
elsif n=9999 then
  n:=0;a<=not a;
end if ;
end if;
end process;
cp<=a;
end des;