📄 music.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity music is
port(clk20mhz :in std_logic;
clk1000hz:in std_logic;
sw :in std_logic;
spkout :out std_logic);
end;
architecture behav of music is
component sepratef
port(clk,sw: in std_logic;
clk125f: out std_logic);
end component;
component rhythmer
port(clk: in std_logic;
tonecode:out integer range 0 to 21);
end component;
component tonetaba
port(tonecodein: in integer range 0 to 21;
musicfreqout:out integer range 0 to 2047);
end component;
component speakera
port(clk: in std_logic;
musicfreqin:in integer range 0 to 2047;
spks: out std_logic);
end component;
signal clk125f:std_logic;
signal musicfreqin,musicfreqout: integer range 0 to 2047;
signal tonecode: integer range 0 to 21;
begin
u0:sepratef port map(clk=>clk1000hz,sw=>sw,clk125f=>clk125f);
u1:rhythmer port map(clk=>clk125f,tonecode=>tonecode);
u2:tonetaba port map(tonecodein=>tonecode,musicfreqout=>musicfreqout);
u3:speakera port map(clk=>clk20mhz,musicfreqin=>musicfreqout,spks=>spkout);
end;
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