speakera.vhd

来自「一个使用VHDL编写的音乐芯片的程序有很好的使用价值」· VHDL 代码 · 共 43 行

library ieee;
use ieee.std_logic_1164.all;
entity speakera is
    port(clk:        in std_logic;  --20mhz
         musicfreqin:in integer range 0 to 2047;
         spks:       out std_logic);
end;

architecture behav of speakera is 
    signal preclk:std_logic;
    signal fullspkd:std_logic;
begin
  divideclk:process(clk)
     variable count20: integer range 0 to 25;
    begin
     preclk<='0';
     if count20>20 then preclk<='1'; count20:=0;
     elsif clk'event and clk='1' then count20:=count20+1;
     end if;
  end process;
 genspks:process(preclk,musicfreqin)
 variable countf: integer range 0 to 2047;
begin
     if preclk'event and preclk='1' then 
       if countf=2047 then
        countf:=musicfreqin;
        fullspkd<='1';
       else countf:=countf+1;
            fullspkd<='0';
       end if;
     end if;
end process;
delayspks:process(fullspkd)
variable count2: std_logic;
begin
   if fullspkd'event and fullspkd='1' then
       count2:=not count2;
          if count2='1' then spks<='1';
          else spks<='0';end if;
          end if;
    end process;
end;