📄 sepratef.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity sepratef is
port(clk,sw: in std_logic; --1000hz
clk125f:out std_logic);--8 or 4hz putout
end;
architecture behav of sepratef is
signal clk8hz:std_logic;
begin
divideclk:process(clk,sw)
variable ff, count125: integer range 0 to 255;
begin
clk8hz<='0'; clk125f<='0';
if sw='0' then ff:=125;else ff:=250;
end if;
if count125>ff then clk8hz<='1'; clk125f<='1'; count125:=0;
elsif clk'event and clk='1' then count125:=count125+1;
end if;
end process;
end;
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