2dfft.vhd

VHDL 关于2DFFT设计程序 u scinode1 &#8764 scinode9.vhd: Every SCI node RTL vhdl code. The details can be

library ieee;
use ieee.std_logic_1164.all;

entity twod_fft is
--port(	reset, clk:		std_logic);
end twod_fft;

architecture spec of twod_fft is
signal reset: std_logic := '0';
signal clk: std_logic := '0';
component scinode1
	port ( reset, clk:	in std_logic;
           vertical_data_in:	in std_logic_vector(15 downto 0);
      	   horizontal_data_in:	in std_logic_vector(15 downto 0);
           vertical_data_out:	out std_logic_vector(15 downto 0);
      	   horizontal_data_out:	out std_logic_vector(15 downto 0);
   		   global_cnt:			in integer range 0 to 110);
end component;

component scinode2
	port ( reset, clk:	in std_logic;
           vertical_data_in:	in std_logic_vector(15 downto 0);
      	   horizontal_data_in:	in std_logic_vector(15 downto 0);
           vertical_data_out:	out std_logic_vector(15 downto 0);
      	   horizontal_data_out:	out std_logic_vector(15 downto 0);
     	   global_cnt:			integer range 0 to 110);
end component;

component scinode3
	port ( reset, clk:	in std_logic;
           vertical_data_in:	in std_logic_vector(15 downto 0);
      	   horizontal_data_in:	in std_logic_vector(15 downto 0);
           vertical_data_out:	out std_logic_vector(15 downto 0);
      	   horizontal_data_out:	out std_logic_vector(15 downto 0);
     	   global_cnt:			integer range 0 to 110);
end component;

component scinode4
	port ( reset, clk:	in std_logic;
           vertical_data_in:	in std_logic_vector(15 downto 0);
      	   horizontal_data_in:	in std_logic_vector(15 downto 0);
           vertical_data_out:	out std_logic_vector(15 downto 0);
      	   horizontal_data_out:	out std_logic_vector(15 downto 0);
      global_cnt:			in integer range 0 to 110);
end component;

component scinode5
	port ( reset, clk:	in std_logic;
           vertical_data_in:	in std_logic_vector(15 downto 0);
      	   horizontal_data_in:	in std_logic_vector(15 downto 0);
           vertical_data_out:	out std_logic_vector(15 downto 0);
      	   horizontal_data_out:	out std_logic_vector(15 downto 0);
     	   global_cnt:			integer range 0 to 110);
end component;

component scinode6
	port ( reset, clk:	in std_logic;
           vertical_data_in:	in std_logic_vector(15 downto 0);
      	   horizontal_data_in:	in std_logic_vector(15 downto 0);
           vertical_data_out:	out std_logic_vector(15 downto 0);
      	   horizontal_data_out:	out std_logic_vector(15 downto 0);
     	   global_cnt:			integer range 0 to 110);
end component;

component scinode7
port( reset, clk:	in std_logic;
      vertical_data_in:	in std_logic_vector(15 downto 0);
      horizontal_data_in:	in std_logic_vector(15 downto 0);
      vertical_data_out:	out std_logic_vector(15 downto 0);
      horizontal_data_out:	out std_logic_vector(15 downto 0);
      global_cnt:			in integer range 0 to 110);
end component;

component scinode8
port( reset, clk:	in std_logic;
      vertical_data_in:	in std_logic_vector(15 downto 0);
      horizontal_data_in:	in std_logic_vector(15 downto 0);
      vertical_data_out:	out std_logic_vector(15 downto 0);
      horizontal_data_out:	out std_logic_vector(15 downto 0);
      global_cnt:			in integer range 0 to 110);
end component;

component scinode9
port( reset, clk:	in std_logic;
      vertical_data_in:	in std_logic_vector(15 downto 0);
      horizontal_data_in:	in std_logic_vector(15 downto 0);
      vertical_data_out:	out std_logic_vector(15 downto 0);
      horizontal_data_out:	out std_logic_vector(15 downto 0);
      global_cnt:			in integer range 0 to 110);
end component;

signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12: std_logic_vector(15 downto 0);
signal n13, n14, n15, n16, n17, n18: std_logic_vector(15 downto 0);
signal cnt:			integer range 0 to 5;
signal global_cnt:	integer range 0 to 110;

begin
   	
   	clk <= not clk after 5 ns;
	process
	begin
   		reset	 <= '1';
   		wait for 100 ns;
   		reset	 <= '0';   
   		wait for 1000 us; 	
	end process;

	node1: scinode1
		port map( reset, clk, n10, n1, n11, n2, global_cnt );
		
	node2: scinode2
		port map( reset, clk, n13, n2, n14, n3, global_cnt );
		
	node3: scinode3
		port map( reset, clk, n16, n3, n17, n1, global_cnt );
		
	node4: scinode4
		port map( reset, clk, n11, n4, n12, n5, global_cnt );
		
	node5: scinode5
		port map( reset, clk, n14, n5, n15, n6, global_cnt );
		
	node6: scinode6
		port map( reset, clk, n17, n6, n18, n4, global_cnt );
		
	node7: scinode7
		port map( reset, clk, n12, n7, n10, n8, global_cnt );
		
	node8: scinode8
		port map( reset, clk, n15, n8, n13, n9, global_cnt );
		
	node9: scinode9
		port map( reset, clk, n18, n9, n16, n7, global_cnt );
				
process( clk, reset )
begin
	if( reset = '1' ) then
		global_cnt <= 0;
		cnt <= 0;
--		n1 <= "0000000000000000";
--		n2 <= "1111111111111111";
	elsif( rising_edge( clk ) ) then
		if( cnt = 5 ) then
			cnt <= 0;
		else
			cnt <= cnt + 1;
		end if;
		if( cnt = 3 ) then
			global_cnt <= global_cnt + 1;
		end if;
	end if;
end process;		

end spec;
		
configuration test of twod_fft is
        for spec
        end for;
end test;