structure.txt

we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity structure_modual is
    Port ( --input signal 
		   clk        	 : in std_logic;
		   bits_in		 : in std_logic_vector(7 downto 0);
             clk_set 	     : in std_logic;
           
		   jam_enable 	 : in std_logic;
		   
		   group_set	 : in std_logic ;
		   --bits_buffer	 : buffer std_logic_vector(7 downto 0);
		   --group_num_decimal:	buffer integer range 1 to 20;
		   --output_buffer:       buffer std_logic_vector (3 downto 0);
             --output signal
		   z_out      	 : out std_logic;					 
             q      	 : out std_logic_vector(3 downto 0));
end entity structure_modual;

architecture structural of structure_modual is

component newclock
	--port (8bits_in,clk_set,clk,8bits_buffer,newclk_en);
	Port (	clk_binary:in std_logic_vector(7 downto 0);
			clk_set	:in std_logic;
			clk : in std_logic;-- clock input 
			binary :buffer std_logic_vector(7 downto 0);
    		newclk_en: out std_logic);
end component ;
component generic_counter
	--port (clk,newclk_en,select_group,group_set,jam,jam_enable,group_num_decimal,output_buffer,z_out,q);
	port (	clk:			in std_logic; --50Mhz:internal clock
		newclk_en_g:		in std_logic ;--the newly get changable clock
		 bits_in:			in std_logic_vector (7 downto 0);
		group_set_g:		in std_logic ;
		
		jam_enable_g:		in std_logic ;
		group_num_decimal:	buffer integer range 1 to 20;
		output_buffer:      buffer std_logic_vector (3 downto 0);
		z_out_g :			out std_logic ;
		q_g:				out std_logic_vector (3 downto 0));
end component ;

signal newclk_en:std_logic;  
--signal jam:std_logic_vector(3 downto 0);
--signal select_group:std_logic_vector (4 downto 0);

--signal 8bits:std_logic_vector (7 downto 0);
--alias jam:std_logic_vector(3 downto 0) is bits_in(3 downto 0);
--alias select_group:std_logic_vector(3 downto 0) is bits_in(7 downto 4); 
begin
--8bits<=8bits_in;
get_clock:newclock

--g0:entity work.newclock(behavioral)
port map (clk_binary=>bits_in,clk_set=>clk_set,clk=>clk,newclk_en=>newclk_en);
counter:generic_counter

--g1:entity work.generic_counter(behavioral)
port map (clk=>clk,newclk_en_g=>newclk_en,bits_in=>bits_in,group_set_g=>group_set,jam_enable_g=>jam_enable,z_out_g=>z_out,q_g=>q);

end structural;