generic_counter.txt

we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity generic_counter is
	
port (	clk:				in std_logic; --50Mhz:internal clock
		newclk_en_g:		in std_logic ;--the newly get changable clock
		bits_in:			in std_logic_vector (7 downto 0);
		--select_group_g:		in std_logic_vector(4 downto 0); 
		group_set_g:		in std_logic ;
		--jam_g:				in std_logic_vector (3 downto 0);
		jam_enable_g:		in std_logic ;
		group_num_decimal:	buffer integer range 1 to 20;
		--k:				buffer integer range 1 to 16;	
		--id:				buffer integer range 1 to 16;
		output_buffer:      buffer std_logic_vector (3 downto 0);
		z_out_g :			out std_logic ;
		q_g:				out std_logic_vector (3 downto 0));
end generic_counter;

architecture behaviour of generic_counter is

type state_table20x16 is array(1 to 20,1 to 16)of std_logic_vector(3 downto 0);
type state_table20x7  is array(1 to 20,1 to 7)of std_logic_vector (3 downto 0);

--signal state_table:state_table20x16;
--signal to_allowed_states:state_table20x7;

signal n:integer range 1 to 16; 

--signal id:integer range 1 to 16;

signal k:integer range 1 to 16;
--signal s_id:integer range 1 to 16;
signal jam:std_logic_vector (3 downto 0);
signal jam_change:std_logic;
signal group_change:std_logic ;
signal group_num:std_logic_vector(4 downto 0);
signal state:std_logic_vector (3 downto 0);
constant s0:std_logic_vector(3 downto 0):="0000";
constant s1:std_logic_vector(3 downto 0):="0001";
constant s2:std_logic_vector(3 downto 0):="0010";
constant s3:std_logic_vector(3 downto 0):="0011";
constant s4:std_logic_vector(3 downto 0):="0100";
constant s5:std_logic_vector(3 downto 0):="0101";
constant s6:std_logic_vector(3 downto 0):="0110";
constant s7:std_logic_vector(3 downto 0):="0111";
constant s8:std_logic_vector(3 downto 0):="1000";		  
constant s9:std_logic_vector(3 downto 0):="1001";
constant s10:std_logic_vector(3 downto 0):="1010";
constant s11:std_logic_vector(3 downto 0):="1011";
constant s12:std_logic_vector(3 downto 0):="1100";
constant s13:std_logic_vector(3 downto 0):="1101";
constant s14:std_logic_vector(3 downto 0):="1110";
constant s15:std_logic_vector(3 downto 0):="1111";

constant st:state_table20x16:=(
(s13,s12,s11,s9,s8,s7,s5,s4,s2,s0,s1,s3,s6,s10,s14,s15),--1
(s15,s14,s13,s12,s11,s10,s8,s7,s5,s3,s1,s0,s2,s4,s6,s9),--2
(s15,s14,s13,s12,s11,s10,s8,s7,s5,s4,s2,s1,s0,s3,s6,s9),--3
(s13,s12,s11,s9,s8,s7,s5,s4,s3,s0,s1,s2,s6,s10,s14,s15),--4
(s15,s14,s13,s12,s10,s9,s8,s6,s4,s2,s1,s0,s3,s5,s7,s11),--5
(s15,s14,s13,s12,s11,s9,s8,s6,s5,s3,s2,s1,s0,s4,s7,s10),--6
(s13,s12,s11,s9,s8,s7,s6,s5,s3,s0,s1,s2,s4,s10,s14,s15),--7
(s15,s14,s13,s11,s10,s9,s7,s5,s3,s2,s1,s0,s4,s6,s8,s12),--8
(s15,s14,s13,s12,s10,s9,s7,s6,s4,s3,s2,s1,s0,s5,s8,s11),--9
(s13,s12,s11,s10,s8,s7,s6,s5,s3,s0,s1,s2,s4,s9,s14,s15),--10
(s15,s14,s12,s11,s10,s8,s6,s4,s3,s2,s1,s0,s5,s7,s9,s13),--11
(s15,s14,s13,s11,s10,s8,s7,s5,s4,s3,s2,s1,s0,s6,s9,s12),--12
(s14,s12,s11,s10,s8,s7,s6,s5,s3,s0,s1,s2,s4,s9,s13,s15),--13
(s15,s13,s12,s10,s8,s6,s5,s4,s3,s2,s1,s0,s7,s9,s11,s14),--14
(s15,s14,s12,s11,s9,s8,s6,s5,s4,s3,s2,s1,s0,s7,s10,s13),--15
(s14,s13,s11,s10,s8,s7,s6,s5,s3,s0,s1,s2,s4,s9,s12,s15),--16
(s14,s13,s11,s9,s7,s6,s5,s4,s3,s2,s1,s0,s8,s10,s12,s15),--17
(s15,s13,s12,s10,s9,s7,s6,s5,s4,s3,s2,s1,s0,s8,s11,s14),--18
(s15,s14,s13,s11,s9,s7,s5,s3,s1,s0,s2,s4,s6,s8,s10,s12),--19
(s15,s14,s13,s12,s11,s9,s8,s7,s5,s3,s1,s0,s2,s4,s6,s10));--20

constant to_states:state_table20x7:=(
(s7,s5,s4,s12,s11,s11,s9),	--1
(s15,s13,s3,s8,s7,s0,s0),	 --2
(s1,s2,s5,s7,s0,s0,s0),		 --3
(s13,s3,s5,s13,s12,s9,s8),	 --4
(s6,s15,s15,s15,s10,s0,s0),	 --5
(s8,s15,s15,s11,s0,s0,s0),	  --6
(s3,s5,s7,s13,s8,s7,s3),	  --7
(s10,s9,s7,s5,s7,s0,s0),	  --8
(s13,s15,s15,s10,s0,s0,s0),	  --9
(s13,s13,s13,s13,s13,s13,s13),--10
(s15,s15,s15,s15,s15,s0,s0),   --11
(s15,s15,s15,s15,s0,s0,s0),	   --12
(s12,s12,s12,s12,s12,s12,s12), --13
(s13,s13,s13,s13,s13,s0,s0),   --14
(s8,s8,s8,s8,s0,s0,s0),			--15
(s7,s7,s7,s7,s7,s7,s7),			--16
(s9,s9,s9,s9,s9,s0,s0),			--17
(s4,s4,s4,s4,s0,s0,s0),			--18
(s3,s3,s3,s3,s3,s3,s3),			--19
(s1,s1,s1,s1,s1,s0,s0)			--20
);

begin

process(clk)						 --read group number
begin
if (rising_edge(clk)) then	
	group_change<=group_set_g;
	if group_change='1'then
		group_num(4 downto 0)<=bits_in(4 downto 0);
	end if;
end if;	
end process;

process(clk)			   --read jam
begin
if(rising_edge(clk))then 
	jam_change<=jam_enable_g;
	if (jam_change='1')then
	jam<=bits_in(3 downto 0);	
	end if;
end if;
end process;

--select the required group
process(clk)
begin
if((rising_edge(clk))and(group_change='1'))then	
case group_num is

when "00001"=>
group_num_decimal<=1;
n<=9;
output_buffer<="1101";
when "00010"=>	
group_num_decimal<=2;
n<=11;
 output_buffer<="1101";
when "00011"=>
 group_num_decimal<=3;
n<=12;
 output_buffer<="1101";
when "00100"=>
group_num_decimal<=4;
n<=9;
output_buffer<="1100";
when "00101"=>
group_num_decimal<=5;	
n<=11;
output_buffer<="1100";
when "00110"=>
group_num_decimal<=6;
n<=12; 
output_buffer<="1100";
when "00111"=>
group_num_decimal<=7;
n<=9;
 output_buffer<="1011";
when "01000"=>
group_num_decimal<=8;
n<=11;
 output_buffer<="1011";
when"01001" =>
group_num_decimal<=9;
n<=12;
 output_buffer<="1010";
when "01010"=>
group_num_decimal<=10;
n<=9;
 output_buffer<="1010";
when "01011"=>
group_num_decimal<=11;
n<=11;
output_buffer<="1010";
when "01100"=>
group_num_decimal<=12;
n<=12;
 output_buffer<="1010";
when "01101"=>
group_num_decimal<=13;
n<=9;
output_buffer<="0111";
when "01110"=>
group_num_decimal<=14;
n<=11; 
output_buffer<="1000";
when "01111"=>
group_num_decimal<=15;
n<=12;
output_buffer<="1000";
when "10000"=>
group_num_decimal<=16;
n<=9;
 output_buffer<="0110";
when "10001"=>
group_num_decimal<=17;	
n<=11;
output_buffer<="0110";
when "10010"=>
group_num_decimal<=18;	
n<=12; 
output_buffer<="0110";
when "10011"=>
group_num_decimal<=19;
n<=9;
output_buffer<="1101";
when "10100"=>
group_num_decimal<=20;
n<=11;
output_buffer<="1100";
when others=>
group_num_decimal<=5;	
n<=11;
output_buffer<="1100";
end case;
end if;
end process;

process(clk,newclk_en_g)
variable jam_id:integer range 1 to 16;
variable id:integer range 1 to 16;	 
--variable k:integer range 1 to 16;
begin
if(rising_edge(clk)and (jam_change='1'))then
gen1:	for i in 1 to 16 loop
			if (st(group_num_decimal,i)=jam)then 
			jam_id:=i;--jam_id :an integer to record the id of the state vector;
			exit;
			end if;
			--jam<="uuuu"	;
		end loop gen1;
		
		if	jam_id>n then		  --it is a not-allocted state
		state<=to_states(group_num_decimal,(jam_id-n));		
gen2:		for i in 1 to 12 loop
				id:=i;    --find the id of the state changed into
				exit when(st(group_num_decimal,i)=state);					
			end loop gen2;
		else
			id:=jam_id  ;
			id:=id+1;
			if(id=n+1)then
			id:=1;
			end if;
		end if;
k<=id;
end if;

end process;
--
process(clk,newclk_en_g)
variable s_id:integer range 1 to 16;
begin 	 
if(jam_change='1')then
	s_id:=k;
	q_g<=jam;
--end if;
--elsif((newclk_en_g'event and newclk_en_g='1')and(jam_change='1'))then
--	q_g<=jam;

elsif((newclk_en_g'event and newclk_en_g='1')and(jam_change='0'))then
							 --it is a a allocated state
	q_g<=st(group_num_decimal,s_id);
		
		if(output_buffer=st(group_num_decimal,s_id))then z_out_g<='1';
		else z_out_g<='0';
		end if;	
		s_id:=s_id+1;
		if(s_id=n+1)then
		s_id:=1;
		end if;
		--if(s_id<n+1)then s_id<=s_id+1;
		--else s_id<=1;
		--end if;
end if;
--end if;

end process;

end behaviour;