gaofeicounter.txt

we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity gaofeicounter is
    Port (jam_enable:in std_logic;
    		jam:in std_logic_vector(3 downto 0);
    		clk : in std_logic;                      -- clock input
    		z_out: out std_logic;
		    q :out std_logic_vector(3 downto 0));
end gaofeicounter;

architecture Behavioral of gaofeicounter is
--type states is(,,,,,,,,,,,,,,);

signal clk50				: std_logic ;
signal mhertz_count		: std_logic_vector(11 downto 0) ;	-- Mhz Counter
signal hertz_count		: std_logic_vector(13 downto 0) ;	-- KHz Counter
signal mhertz_en			: std_logic ;	-- MHz internal flag
signal hertz_en			: std_logic ;	-- Hz internal flag
signal next_state:std_logic_vector(3 downto 0);
constant s0:std_logic_vector(3 downto 0):="0000";
constant s1:std_logic_vector(3 downto 0):="0001";
constant s2:std_logic_vector(3 downto 0):="0010";
constant s3:std_logic_vector(3 downto 0):="0011";
constant s4:std_logic_vector(3 downto 0):="0100";
constant s5:std_logic_vector(3 downto 0):="0101";
constant s6:std_logic_vector(3 downto 0):="0110";
constant s7:std_logic_vector(3 downto 0):="0111";
constant s8:std_logic_vector(3 downto 0):="1000";		  
constant s9:std_logic_vector(3 downto 0):="1001";
constant s10:std_logic_vector(3 downto 0):="1010";
constant s11:std_logic_vector(3 downto 0):="1011";
constant s12:std_logic_vector(3 downto 0):="1100";
constant s13:std_logic_vector(3 downto 0):="1101";
constant s14:std_logic_vector(3 downto 0):="1110";
constant s15:std_logic_vector(3 downto 0):="1111";
begin

clk50<=clk;	-- internal signals linkes to i/o

-- defines 1Mhz signal from 50MHz clock
process (clk50)
begin
if clk50'event and clk50 = '1' then
	mhertz_count <= mhertz_count + 1 ;
	if mhertz_count = "110010000000" then
		mhertz_en <= '1' ;
		mhertz_count <= (others => '0') ;
	else 
		mhertz_en <= '0' ;
	end if ;
end if ;
end process ;												

-- defines 1hz signal from 1Mhz signal
process (clk50)
begin
if clk50'event and clk50 = '1' then
	if mhertz_en = '1' then
		hertz_count <= hertz_count + 1 ;
		if hertz_count = "10011100010000" then
			hertz_en <= '1' ;
			hertz_count <= (others => '0') ;
		else
			hertz_en <= '0' ;
		end if ;
	else
		hertz_en <= '0' ;
	end if ;
end if ;
end process ;

process(hertz_en,jam_enable,jam)
begin
if(jam_enable='1')then
--q<=jam;
next_state<=jam;
elsif((hertz_en'event and hertz_en='1')and(jam_enable='0'))then
case next_state is
when	s0=>next_state<=s6;--not
when	s1=>next_state<=s15;
when	s2=>next_state<=s1;	 
when	s3=>next_state<=s15;--not
when	s4=>next_state<=s2;
when	s5=>next_state<=s15;--not
when	s6=>next_state<=s4;
when	s7=>next_state<=s15;--not 
when	s8=>next_state<=s6;
when	s9=>next_state<=s8;
when	s10=>next_state<=s9;
when	s11=>next_state<=s10;--not allowed states
when    s12=>next_state<=s10;
			 
when    s13=>next_state<=s12;					
when	s14=>next_state<=s13;
when	s15=>next_state<=s14;--allowed states
when others=>next_state<="----";
end case;
end if;
end process;

process(hertz_en)
begin
if(hertz_en'event and hertz_en='1')then
	if(next_state=s12)then
	z_out<='1';
	else z_out<='0';
	end if;

	q<=next_state;
--present_state<=next_state;

end if; 
end process;

end Behavioral;