structure_modual.txt

we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity structure_modual is
    Port ( clk_binary : in std_logic_vector(7 downto 0);
           clk_set : in std_logic;
           clk : in std_logic;
		 binary:buffer std_logic_vector(7 downto 0);
           jam_enable : in std_logic;
           --reset : in std_logic;
           z_out : out std_logic;
           q : out std_logic_vector(3 downto 0));
end entity structure_modual;

architecture structural of structure_modual is
signal newclk_en:std_logic;  
signal jam:std_logic_vector(3 downto 0);
begin
jam<=clk_binary(3 downto 0);
g0:entity work.newclock(behavioral)
	port map (clk_binary,clk_set,clk,binary,newclk_en);
g1:entity work.gaofeicounter(behavioral)
	port map (jam,jam_enable,newclk_en,z_out,q);

end structural;