gaofeicounter.txt

we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity gaofeicounter is
    Port ( jam:in std_logic_vector(3 downto 0);
    		 jam_enable:in std_logic;
    		 newclk_en : in std_logic;-- clock input
			--reset:in std_logic ;
    		z_out: out std_logic;
		q :out std_logic_vector(3 downto 0));
end gaofeicounter;	  

architecture Behavioral of gaofeicounter is

--signal flag:std_logic ;
signal next_state:std_logic_vector(3 downto 0);
constant s0:std_logic_vector(3 downto 0):="0000";
constant s1:std_logic_vector(3 downto 0):="0001";
constant s2:std_logic_vector(3 downto 0):="0010";
constant s3:std_logic_vector(3 downto 0):="0011";
constant s4:std_logic_vector(3 downto 0):="0100";
constant s5:std_logic_vector(3 downto 0):="0101";
constant s6:std_logic_vector(3 downto 0):="0110";
constant s7:std_logic_vector(3 downto 0):="0111";
constant s8:std_logic_vector(3 downto 0):="1000";		  
constant s9:std_logic_vector(3 downto 0):="1001";
constant s10:std_logic_vector(3 downto 0):="1010";
constant s11:std_logic_vector(3 downto 0):="1011";
constant s12:std_logic_vector(3 downto 0):="1100";
constant s13:std_logic_vector(3 downto 0):="1101";
constant s14:std_logic_vector(3 downto 0):="1110";
constant s15:std_logic_vector(3 downto 0):="1111";

begin
process(newclk_en,jam_enable,jam)
begin
--if reset = '1' then
--flag <= '0';
if(jam_enable='1')then
next_state<=jam;
--flag<='1';
elsif((newclk_en'event and newclk_en='1')and(jam_enable='0'))then
case next_state is
when	s0=>next_state<=s6;--not
when	s1=>next_state<=s15;
when	s2=>next_state<=s1;	 
when	s3=>next_state<=s15;--not
when	s4=>next_state<=s2;
when	s5=>next_state<=s15;--not
when	s6=>next_state<=s4;
when	s7=>next_state<=s15;--not 
when	s8=>next_state<=s6;
when	s9=>next_state<=s8;
when	s10=>next_state<=s9;
when	s11=>next_state<=s10;--not allowed states
when    s12=>next_state<=s10;
			 
when    s13=>next_state<=s12;					
when	s14=>next_state<=s13;
when	s15=>next_state<=s14;--allowed states
when others=>next_state<="----";
end case;
end if;

--if(reset='1')then
--	flag<='0';
--	end if;


end process;

process(newclk_en)
begin
if(newclk_en'event and newclk_en='1')then
	if(next_state=s12)then
	z_out<='1';
	else z_out<='0';
	end if;

q<=next_state;
end if; 
end process;


end Behavioral;