structure_modual.txt

we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity structure_modual is

    Port ( 
		   clk        	 : in std_logic;
		   bits_in		 : in std_logic_vector(7 downto 0);
             clk_set 	     : in std_logic;
           
		   jam_enable 	 : in std_logic;
		   
		   --group_set	 : in std_logic ;
		   
		   z_out      	 : out std_logic;					 
             q      	 : out std_logic_vector(3 downto 0));
end entity structure_modual;

architecture structural of structure_modual is

component newclock
	
	Port (	clk_binary:in std_logic_vector(7 downto 0);
			clk_set	:in std_logic;
			clk : in std_logic;-- clock input 
			binary :buffer std_logic_vector(7 downto 0);
    		newclk_en: out std_logic);
end component ;

component generic_counter
	generic(group_num:positive);	
	 port (	clk:				      in std_logic; 			   --50Mhz:internal clock
		newclk_en_g:	      in std_logic; 	    --the newly get changable clock
		bits_in:		         in std_logic_vector (7 downto 0);
--8-bit binary read in through 7 switches 
		--group_set_g:		      in std_logic; 			    --select the right group
		jam_enable_g:	      in std_logic; 			-- set the not-allowed states
		--group_num_decimal:	  buffer integer range 1 to 20; --decimal person number 
--to identify each group
		output_buffer:        buffer std_logic_vector (3 downto 0);
--store the highlight number
		z_out_g :			  out std_logic; 		-- used to highlight the the state 
--"1100" according to requirement in the project outline
		q_g:			     out std_logic_vector (3 downto 0)); 	--out put the
--next counter state
end component ;

signal newclk_en:std_logic;  
 
begin

get_clock:newclock

--g0:entity work.newclock(behavioral)
port map (clk_binary=>bits_in,clk_set=>clk_set,clk=>clk,newclk_en=>newclk_en);
counter:generic_counter

--g1:entity work.generic_counter(behavioral)
generic map(group_num=>5)
port map (clk=>clk,newclk_en_g=>newclk_en,bits_in=>bits_in,jam_enable_g=>jam_enable,z_out_g=>z_out,q_g=>q);

end structural;