newclock.txt

we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
	  
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity newclock is 
    Port (	clk_binary:in std_logic_vector(7 downto 0);
			clk_set	:in std_logic;
			clk : in std_logic;-- clock input 
			binary :buffer std_logic_vector(7 downto 0);
    		newclk_en: out std_logic);
end newclock;
		    
architecture Behavioral of newclock is
--signal clk50 			:std_logic;
signal mhertz_count		: std_logic_vector(8 downto 0) ;	-- Mhz Counter
signal hertz_count		: std_logic_vector(14 downto 0) ;	-- KHz Counter
signal mhertz_en		: std_logic ;	-- MHz internal flag
signal hertz_en			: std_logic ;	-- Hz internal flag

signal cmp_binary	    : std_logic_vector(7 downto 0);
signal clknew_temp		:std_logic ;
signal clk_change       :std_logic;

begin

--process(clk)
--begin


--end if;
--end process;


--binary<=clk_binary when(clk_change='1') ;


------------------------------------------------------
-- defines 0.1Mhz signal from 50MHz clock
process (clk)
begin
if (rising_edge(clk)) then
	mhertz_count <= mhertz_count + 1 ;
	if mhertz_count ="111110100"  then
		mhertz_en <= '1' ;
		mhertz_count <= (others => '0') ;
	else 
		mhertz_en <= '0' ;
	end if ;
end if ;
end process ;												

-- defines 4hz signal from 0.1Mhz signal
process (clk)
begin
if (rising_edge(clk)) then
	if mhertz_en = '1' then
		hertz_count <= hertz_count + 1 ;
		if hertz_count ="110000110101000" then --T=0.25s(4hz)
			hertz_en <= '1' ;
			hertz_count <= (others => '0') ;
		else
			hertz_en <= '0' ;
		end if ;
	else
		hertz_en <= '0' ;
	end if ;
end if ;
end process ;

--caculate the new clock based on the binary input
--process(clk_set) 
--begin
--if (clk_set='1')then

--fg<='1';
--end if;
--end process;

------------------------------------------------------

process(clk,hertz_en)
begin 
if (rising_edge(clk)) then
     clk_change<=clk_set ;
	if	clk_change='1' then 
		binary<=clk_binary;
		cmp_binary<="00000000"; 
	elsif hertz_en = '1' then
				cmp_binary<=cmp_binary+1;
				if cmp_binary=binary then
				clknew_temp<='1'; 
				cmp_binary<=(others=>'0');
				else
		     	clknew_temp<='0';
				end if;
	else 
		clknew_temp<='0';
		
	end if;
	--end if;
end if;

end process;

newclk_en<=clknew_temp;

end architecture Behavioral;