p7segment.rpt

卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能

datain0  : INPUT;
datain1  : INPUT;
datain2  : INPUT;
datain3  : INPUT;

-- Node name is 'out0' 
-- Equation name is 'out0', type is output 
out0     =  _LC2_B20;

-- Node name is 'out1' 
-- Equation name is 'out1', type is output 
out1     =  _LC3_B20;

-- Node name is 'out2' 
-- Equation name is 'out2', type is output 
out2     =  _LC1_B13;

-- Node name is 'out3' 
-- Equation name is 'out3', type is output 
out3     =  _LC2_B13;

-- Node name is 'out4' 
-- Equation name is 'out4', type is output 
out4     =  _LC5_B20;

-- Node name is 'out5' 
-- Equation name is 'out5', type is output 
out5     =  _LC7_B16;

-- Node name is 'out6' 
-- Equation name is 'out6', type is output 
out6     =  _LC1_B20;

-- Node name is ':48' 
-- Equation name is '_LC3_B16', type is buried 
_LC3_B16 = LCELL( _EQ001);
  _EQ001 =  datain0 &  datain1 & !datain2 & !datain3;

-- Node name is ':60' 
-- Equation name is '_LC4_B23', type is buried 
_LC4_B23 = LCELL( _EQ002);
  _EQ002 = !datain0 & !datain1 &  datain2 & !datain3;

-- Node name is ':144' 
-- Equation name is '_LC3_B13', type is buried 
_LC3_B13 = LCELL( _EQ003);
  _EQ003 =  datain0 &  datain1 & !datain2 &  datain3;

-- Node name is ':180' 
-- Equation name is '_LC6_B23', type is buried 
_LC6_B23 = LCELL( _EQ004);
  _EQ004 = !datain0 &  datain1 &  datain2 &  datain3;

-- Node name is ':192' 
-- Equation name is '_LC6_B20', type is buried 
_LC6_B20 = LCELL( _EQ005);
  _EQ005 =  datain0 &  datain1 &  datain2 &  datain3;

-- Node name is '~218~1' 
-- Equation name is '~218~1', location is LC3_B23, type is buried.
-- synthesized logic cell 
!_LC3_B23 = _LC3_B23~NOT;
_LC3_B23~NOT = LCELL( _EQ006);
  _EQ006 = !datain0 &  datain1 &  datain2 & !datain3
         #  datain0 & !datain1 &  datain2 & !datain3;

-- Node name is '~218~2' 
-- Equation name is '~218~2', location is LC4_B20, type is buried.
-- synthesized logic cell 
_LC4_B20 = LCELL( _EQ007);
  _EQ007 = !_LC2_B16 & !_LC6_B20;

-- Node name is ':218' 
-- Equation name is '_LC2_B23', type is buried 
!_LC2_B23 = _LC2_B23~NOT;
_LC2_B23~NOT = LCELL( _EQ008);
  _EQ008 = !_LC1_B16 & !_LC3_B13 &  _LC3_B23 &  _LC4_B20;

-- Node name is '~227~1' 
-- Equation name is '~227~1', location is LC2_B16, type is buried.
-- synthesized logic cell 
!_LC2_B16 = _LC2_B16~NOT;
_LC2_B16~NOT = LCELL( _EQ009);
  _EQ009 = !datain3
         # !datain2
         #  datain0;

-- Node name is '~227~2' 
-- Equation name is '~227~2', location is LC5_B23, type is buried.
-- synthesized logic cell 
_LC5_B23 = LCELL( _EQ010);
  _EQ010 = !datain0 &  datain1 & !datain2 &  datain3
         #  datain0 & !datain1 & !datain2 &  datain3;

-- Node name is '~227~3' 
-- Equation name is '~227~3', location is LC8_B20, type is buried.
-- synthesized logic cell 
_LC8_B20 = LCELL( _EQ011);
  _EQ011 = !datain0 & !datain2
         # !datain1 & !datain2 &  datain3
         #  datain1 & !datain3
         #  datain0 &  datain2 & !datain3;

-- Node name is ':227' 
-- Equation name is '_LC1_B20', type is buried 
_LC1_B20 = LCELL( _EQ012);
  _EQ012 =  _LC1_B20 & !_LC2_B23
         #  _LC8_B20
         # !_LC4_B20;

-- Node name is '~230~1' 
-- Equation name is '~230~1', location is LC1_B16, type is buried.
-- synthesized logic cell 
!_LC1_B16 = _LC1_B16~NOT;
_LC1_B16~NOT = LCELL( _EQ013);
  _EQ013 =  datain0 & !datain1 &  datain2 & !datain3
         # !datain0 &  datain2 &  datain3
         # !datain0 &  datain1 &  datain2
         #  datain1 &  datain2 &  datain3
         #  datain0 &  datain1 &  datain3;

-- Node name is ':230' 
-- Equation name is '_LC7_B16', type is buried 
_LC7_B16 = LCELL( _EQ014);
  _EQ014 = !_LC2_B23 &  _LC7_B16
         #  _LC1_B16;

-- Node name is '~233~1' 
-- Equation name is '~233~1', location is LC7_B20, type is buried.
-- synthesized logic cell 
_LC7_B20 = LCELL( _EQ015);
  _EQ015 = !datain0 & !datain1 & !datain2
         # !datain0 &  datain2 & !datain3
         # !datain1 &  datain2 & !datain3
         # !datain0 & !datain1 & !datain3
         # !datain2 &  datain3;

-- Node name is '~233~2' 
-- Equation name is '~233~2', location is LC4_B13, type is buried.
-- synthesized logic cell 
_LC4_B13 = LCELL( _EQ016);
  _EQ016 =  datain0 &  datain1 & !datain3
         #  datain0 & !datain2 & !datain3
         #  datain0 & !datain1 &  datain2 &  datain3;

-- Node name is ':233' 
-- Equation name is '_LC5_B20', type is buried 
_LC5_B20 = LCELL( _EQ017);
  _EQ017 = !_LC2_B23 &  _LC5_B20
         #  _LC4_B13
         #  _LC7_B20;

-- Node name is '~236~1' 
-- Equation name is '~236~1', location is LC6_B13, type is buried.
-- synthesized logic cell 
_LC6_B13 = LCELL( _EQ018);
  _EQ018 =  datain0 & !datain1 & !datain2 &  datain3
         #  datain0 & !datain1 &  datain2 & !datain3;

-- Node name is '~236~2' 
-- Equation name is '~236~2', location is LC7_B13, type is buried.
-- synthesized logic cell 
_LC7_B13 = LCELL( _EQ019);
  _EQ019 = !datain0 & !datain1 & !datain2
         # !datain0 & !datain2 & !datain3
         #  datain0 & !datain1 &  datain2 &  datain3
         # !datain0 &  datain1 & !datain3;

-- Node name is '~236~3' 
-- Equation name is '~236~3', location is LC8_B13, type is buried.
-- synthesized logic cell 
_LC8_B13 = LCELL( _EQ020);
  _EQ020 =  _LC6_B13
         #  _LC7_B13
         #  _LC2_B16
         #  _LC3_B13;

-- Node name is ':236' 
-- Equation name is '_LC2_B13', type is buried 
_LC2_B13 = LCELL( _EQ021);
  _EQ021 =  _LC2_B13 & !_LC2_B23
         #  _LC8_B13
         #  _LC3_B16;

-- Node name is '~239~1' 
-- Equation name is '~239~1', location is LC5_B13, type is buried.
-- synthesized logic cell 
_LC5_B13 = LCELL( _EQ022);
  _EQ022 =  datain1 &  datain3
         # !datain0 &  datain3
         # !datain0 & !datain2
         #  datain2 &  datain3
         # !datain0 &  datain1;

-- Node name is ':239' 
-- Equation name is '_LC1_B13', type is buried 
_LC1_B13 = LCELL( _EQ023);
  _EQ023 =  _LC1_B13 & !_LC2_B23
         #  _LC5_B13;

-- Node name is ':242' 
-- Equation name is '_LC3_B20', type is buried 
_LC3_B20 = LCELL( _EQ024);
  _EQ024 = !_LC2_B23 &  _LC3_B20
         #  _LC7_B20
         # !_LC4_B20;

-- Node name is '~245~1' 
-- Equation name is '~245~1', location is LC7_B23, type is buried.
-- synthesized logic cell 
_LC7_B23 = LCELL( _EQ025);
  _EQ025 = !datain0 & !datain1 & !datain2 &  datain3
         # !datain0 &  datain1 & !datain2 & !datain3
         #  datain0 & !datain1 &  datain2 &  datain3;

-- Node name is '~245~2' 
-- Equation name is '~245~2', location is LC8_B23, type is buried.
-- synthesized logic cell 
_LC8_B23 = LCELL( _EQ026);
  _EQ026 = !_LC3_B23
         #  _LC5_B23
         #  _LC6_B23
         #  _LC7_B23;

-- Node name is '~245~3' 
-- Equation name is '~245~3', location is LC1_B23, type is buried.
-- synthesized logic cell 
_LC1_B23 = LCELL( _EQ027);
  _EQ027 =  _LC3_B16
         #  _LC3_B13
         #  _LC4_B23
         #  _LC8_B23;

-- Node name is ':245' 
-- Equation name is '_LC2_B20', type is buried 
_LC2_B20 = LCELL( _EQ028);
  _EQ028 =  _LC2_B20 & !_LC2_B23
         #  _LC6_B20
         #  _LC1_B23;



Project Information                         f:\verilog hdl\phone\p7segment.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,745K