📄 account_top.rpt
字号:
C12 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 8/22( 36%)
C14 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
C16 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
C17 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
C19 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
C20 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
C21 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
C22 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 10/22( 45%)
C23 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 44/53 ( 83%)
Total logic cells used: 449/576 ( 77%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.48/4 ( 87%)
Total fan-in: 1564/2304 ( 67%)
Total input pins required: 5
Total input I/O cell registers required: 0
Total output pins required: 40
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 449
Total flipflops required: 114
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 166/ 576 ( 28%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 8 0 2 8 8 8 8 7 8 8 0 8 2 8 8 8 8 5 8 0 8 8 8 160/0
B: 6 8 8 3 8 6 6 5 8 0 6 6 0 7 8 7 8 6 0 8 7 1 8 8 8 146/0
C: 7 8 8 0 8 8 8 8 8 6 8 8 0 0 8 0 6 8 0 7 8 8 7 6 0 143/0
Total: 21 24 24 3 18 22 22 21 24 13 22 22 0 15 18 15 22 22 8 20 23 9 23 22 16 449/0
Device-Specific Information:e:\amj_before_7_22\course\eda\2003year\2003_design\experiment\phone\account_top.rpt
account_top
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
3 - - - 12 INPUT 0 0 0 26 card
1 - - - -- INPUT G 0 0 0 0 clk
7 - - - 03 INPUT 0 0 0 3 decide0
6 - - - 04 INPUT 0 0 0 3 decide1
5 - - - 05 INPUT 0 0 0 4 state
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:e:\amj_before_7_22\course\eda\2003year\2003_design\experiment\phone\account_top.rpt
account_top
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
11 - - - 01 OUTPUT 0 1 0 0 cut
62 - - C -- OUTPUT 0 1 0 0 dismoneyhigh0
61 - - C -- OUTPUT 0 1 0 0 dismoneyhigh1
60 - - C -- OUTPUT 0 1 0 0 dismoneyhigh2
59 - - C -- OUTPUT 0 1 0 0 dismoneyhigh3
58 - - C -- OUTPUT 0 1 0 0 dismoneyhigh4
54 - - - 21 OUTPUT 0 1 0 0 dismoneyhigh5
53 - - - 20 OUTPUT 0 1 0 0 dismoneyhigh6
51 - - - 18 OUTPUT 0 1 0 0 dispmoneylow0
50 - - - 17 OUTPUT 0 1 0 0 dispmoneylow1
49 - - - 16 OUTPUT 0 1 0 0 dispmoneylow2
48 - - - 15 OUTPUT 0 1 0 0 dispmoneylow3
47 - - - 14 OUTPUT 0 1 0 0 dispmoneylow4
39 - - - 11 OUTPUT 0 1 0 0 dispmoneylow5
38 - - - 10 OUTPUT 0 1 0 0 dispmoneylow6
72 - - A -- OUTPUT 0 1 0 0 dispmoneymid0
71 - - A -- OUTPUT 0 1 0 0 dispmoneymid1
70 - - A -- OUTPUT 0 1 0 0 dispmoneymid2
69 - - A -- OUTPUT 0 1 0 0 dispmoneymid3
67 - - B -- OUTPUT 0 1 0 0 dispmoneymid4
66 - - B -- OUTPUT 0 1 0 0 dispmoneymid5
65 - - B -- OUTPUT 0 1 0 0 dispmoneymid6
23 - - B -- OUTPUT 0 1 0 0 disptimehigh0
22 - - B -- OUTPUT 0 1 0 0 disptimehigh1
21 - - B -- OUTPUT 0 1 0 0 disptimehigh2
19 - - A -- OUTPUT 0 1 0 0 disptimehigh3
18 - - A -- OUTPUT 0 1 0 0 disptimehigh4
17 - - A -- OUTPUT 0 1 0 0 disptimehigh5
16 - - A -- OUTPUT 0 1 0 0 disptimehigh6
36 - - - 07 OUTPUT 0 1 0 0 disptimelow0
35 - - - 06 OUTPUT 0 1 0 0 disptimelow1
30 - - C -- OUTPUT 0 1 0 0 disptimelow2
29 - - C -- OUTPUT 0 1 0 0 disptimelow3
28 - - C -- OUTPUT 0 1 0 0 disptimelow4
27 - - C -- OUTPUT 0 1 0 0 disptimelow5
25 - - B -- OUTPUT 0 1 0 0 disptimelow6
73 - - A -- OUTPUT 0 0 0 0 dp4
9 - - - 02 OUTPUT 0 1 0 0 read
10 - - - 01 OUTPUT 0 1 0 0 warn
8 - - - 03 OUTPUT 0 1 0 0 write
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\amj_before_7_22\course\eda\2003year\2003_design\experiment\phone\account_top.rpt
account_top
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - C 22 AND2 0 2 0 5 |account:34|lpm_add_sub:1552|addcore:adder|:167
- 8 - B 03 AND2 0 3 0 4 |account:34|lpm_add_sub:1552|addcore:adder|:175
- 6 - B 09 AND2 0 2 0 1 |account:34|lpm_add_sub:1552|addcore:adder|:179
- 1 - B 09 AND2 0 4 0 2 |account:34|lpm_add_sub:1552|addcore:adder|:187
- 4 - B 09 AND2 0 2 0 3 |account:34|lpm_add_sub:1552|addcore:adder|:191
- 3 - B 02 AND2 0 3 0 4 |account:34|lpm_add_sub:1552|addcore:adder|:199
- 8 - B 02 AND2 0 2 0 1 |account:34|lpm_add_sub:1552|addcore:adder|:203
- 2 - B 02 AND2 0 4 0 4 |account:34|lpm_add_sub:1552|addcore:adder|:211
- 5 - B 17 AND2 0 2 0 1 |account:34|lpm_add_sub:1552|addcore:adder|:215
- 1 - B 17 AND2 0 4 0 4 |account:34|lpm_add_sub:1552|addcore:adder|:223
- 6 - B 20 AND2 0 2 0 1 |account:34|lpm_add_sub:1552|addcore:adder|:227
- 2 - B 20 AND2 0 4 0 3 |account:34|lpm_add_sub:1552|addcore:adder|:235
- 2 - B 15 AND2 0 3 0 3 |account:34|lpm_add_sub:1552|addcore:adder|:243
- 1 - B 15 AND2 0 3 0 3 |account:34|lpm_add_sub:1552|addcore:adder|:251
- 3 - B 13 AND2 0 3 0 3 |account:34|lpm_add_sub:1552|addcore:adder|:259
- 4 - B 13 AND2 0 3 0 3 |account:34|lpm_add_sub:1552|addcore:adder|:267
- 4 - B 22 AND2 0 3 0 3 |account:34|lpm_add_sub:1552|addcore:adder|:275
- 7 - B 22 AND2 0 2 0 1 |account:34|lpm_add_sub:1552|addcore:adder|:279
- 2 - A 07 OR2 0 2 0 1 |account:34|lpm_add_sub:1554|addcore:adder|pcarry1
- 1 - A 12 AND2 ! 0 3 0 6 |account:34|lpm_add_sub:1554|addcore:adder|pcarry2
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