📄 account_top.rpt
字号:
|account:34|lpm_add_sub:1562|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1562|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1563|
|account:34|lpm_add_sub:1563|addcore:adder|
|account:34|lpm_add_sub:1563|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1563|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1563|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1564|
|account:34|lpm_add_sub:1564|addcore:adder|
|account:34|lpm_add_sub:1564|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1564|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1564|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1565|
|account:34|lpm_add_sub:1565|addcore:adder|
|account:34|lpm_add_sub:1565|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1565|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1565|altshift:oflow_ext_latency_ffs|
Device-Specific Information:e:\amj_before_7_22\course\eda\2003year\2003_design\experiment\phone\account_top.rpt
account_top
***** Logic for device 'account_top' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R R R R O
d d E E E E E N
e e V G G S G S S S S F
w c c s C N N E N E E E E _ ^
w r r i i t C c D D R D R R R R # D n
c a e i d d a I a I c I V I V V V V T O C
u r a t e e t N r N l N E N E E E E C N E
t n d e 0 1 e T d T k T D T D D D D K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | dp4
^nCE | 14 72 | dispmoneymid0
#TDI | 15 71 | dispmoneymid1
disptimehigh6 | 16 70 | dispmoneymid2
disptimehigh5 | 17 69 | dispmoneymid3
disptimehigh4 | 18 68 | GNDINT
disptimehigh3 | 19 67 | dispmoneymid4
VCCINT | 20 66 | dispmoneymid5
disptimehigh2 | 21 65 | dispmoneymid6
disptimehigh1 | 22 EPF10K10LC84-3 64 | RESERVED
disptimehigh0 | 23 63 | VCCINT
RESERVED | 24 62 | dismoneyhigh0
disptimelow6 | 25 61 | dismoneyhigh1
GNDINT | 26 60 | dismoneyhigh2
disptimelow5 | 27 59 | dismoneyhigh3
disptimelow4 | 28 58 | dismoneyhigh4
disptimelow3 | 29 57 | #TMS
disptimelow2 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | dismoneyhigh5
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ d d R d d V G G G G V G d d d d d R d
C n i i E i i C N N N N C N i i i i i E i
C C s s S s s C D D D D C D s s s s s S s
I O p p E p p I I I I I I I p p p p p E m
N N t t R m m N N N N N N N m m m m m R o
T F i i V o o T T T T T T T o o o o o V n
I m m E n n n n n n n E e
G e e D e e e e e e e D y
l l y y y y y y y h
o o l l l l l l l i
w w o o o o o o o g
1 0 w w w w w w w h
6 5 4 3 2 1 0 6
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\amj_before_7_22\course\eda\2003year\2003_design\experiment\phone\account_top.rpt
account_top
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 5/22( 22%)
A2 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 11/22( 50%)
A3 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
A5 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
A6 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
A7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
A8 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A9 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
A10 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
A11 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 11/22( 50%)
A12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
A13 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 11/22( 50%)
A14 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
A15 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
A16 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 13/22( 59%)
A17 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
A19 5/ 8( 62%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
A20 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 12/22( 54%)
A22 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
A23 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
A24 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 7/22( 31%)
B1 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
B2 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
B3 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
B4 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
B5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
B6 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B7 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
B8 5/ 8( 62%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
B9 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B11 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B12 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
B13 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
B14 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 10/22( 45%)
B15 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
B16 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
B17 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
B19 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
B20 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
B21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
B22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B23 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
B24 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 5/22( 22%)
C1 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
C2 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 6/22( 27%)
C3 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
C5 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
C6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
C7 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 5/22( 22%)
C8 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 9/22( 40%)
C9 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
C10 6/ 8( 75%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
C11 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 5/22( 22%)
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