account_top.rpt

卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能

Project Informatione:\amj_before_7_22\course\eda\2003year\2003_design\experiment\phone\account_top.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 08/24/2003 20:22:11

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

account_top
      EPF10K10LC84-3       5      40     0    0         0  %    449      77 %

User Pins:                 5      40     0  



Project Informatione:\amj_before_7_22\course\eda\2003year\2003_design\experiment\phone\account_top.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

account_top@3                     card
account_top@1                     clk
account_top@11                    cut
account_top@7                     decide0
account_top@6                     decide1
account_top@62                    dismoneyhigh0
account_top@61                    dismoneyhigh1
account_top@60                    dismoneyhigh2
account_top@59                    dismoneyhigh3
account_top@58                    dismoneyhigh4
account_top@54                    dismoneyhigh5
account_top@53                    dismoneyhigh6
account_top@51                    dispmoneylow0
account_top@50                    dispmoneylow1
account_top@49                    dispmoneylow2
account_top@48                    dispmoneylow3
account_top@47                    dispmoneylow4
account_top@39                    dispmoneylow5
account_top@38                    dispmoneylow6
account_top@72                    dispmoneymid0
account_top@71                    dispmoneymid1
account_top@70                    dispmoneymid2
account_top@69                    dispmoneymid3
account_top@67                    dispmoneymid4
account_top@66                    dispmoneymid5
account_top@65                    dispmoneymid6
account_top@23                    disptimehigh0
account_top@22                    disptimehigh1
account_top@21                    disptimehigh2
account_top@19                    disptimehigh3
account_top@18                    disptimehigh4
account_top@17                    disptimehigh5
account_top@16                    disptimehigh6
account_top@36                    disptimelow0
account_top@35                    disptimelow1
account_top@30                    disptimelow2
account_top@29                    disptimelow3
account_top@28                    disptimelow4
account_top@27                    disptimelow5
account_top@25                    disptimelow6
account_top@73                    dp4
account_top@9                     read
account_top@5                     state
account_top@10                    warn
account_top@8                     write


Project Informatione:\amj_before_7_22\course\eda\2003year\2003_design\experiment\phone\account_top.rpt

** FILE HIERARCHY **



|p7segment:12|
|p7segment:11|
|p7segment:14|
|p7segment:10|
|p7segment:30|
|clkdiv:33|
|clkdiv:33|lpm_add_sub:201|
|clkdiv:33|lpm_add_sub:201|addcore:adder|
|clkdiv:33|lpm_add_sub:201|altshift:result_ext_latency_ffs|
|clkdiv:33|lpm_add_sub:201|altshift:carry_ext_latency_ffs|
|clkdiv:33|lpm_add_sub:201|altshift:oflow_ext_latency_ffs|
|account:34|
|account:34|lpm_add_sub:1552|
|account:34|lpm_add_sub:1552|addcore:adder|
|account:34|lpm_add_sub:1552|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1552|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1552|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1553|
|account:34|lpm_add_sub:1553|addcore:adder|
|account:34|lpm_add_sub:1553|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1553|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1553|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1554|
|account:34|lpm_add_sub:1554|addcore:adder|
|account:34|lpm_add_sub:1554|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1554|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1554|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1555|
|account:34|lpm_add_sub:1555|addcore:adder|
|account:34|lpm_add_sub:1555|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1555|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1555|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1556|
|account:34|lpm_add_sub:1556|addcore:adder|
|account:34|lpm_add_sub:1556|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1556|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1556|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1557|
|account:34|lpm_add_sub:1557|addcore:adder|
|account:34|lpm_add_sub:1557|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1557|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1557|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1558|
|account:34|lpm_add_sub:1558|addcore:adder|
|account:34|lpm_add_sub:1558|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1558|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1558|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1559|
|account:34|lpm_add_sub:1559|addcore:adder|
|account:34|lpm_add_sub:1559|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1559|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1559|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1560|
|account:34|lpm_add_sub:1560|addcore:adder|
|account:34|lpm_add_sub:1560|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1560|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1560|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1561|
|account:34|lpm_add_sub:1561|addcore:adder|
|account:34|lpm_add_sub:1561|altshift:result_ext_latency_ffs|
|account:34|lpm_add_sub:1561|altshift:carry_ext_latency_ffs|
|account:34|lpm_add_sub:1561|altshift:oflow_ext_latency_ffs|
|account:34|lpm_add_sub:1562|
|account:34|lpm_add_sub:1562|addcore:adder|
|account:34|lpm_add_sub:1562|altshift:result_ext_latency_ffs|