phone.flow.rpt

卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能

Flow report for phone
Mon Mar 13 22:38:14 2006
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Flow Summary                                                            ;
+-------------------------+-----------------------------------------------+
; Flow Status             ; Successful - Mon Mar 13 22:38:13 2006         ;
; Quartus II Version      ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ;
; Revision Name           ; phone                                         ;
; Top-level Entity Name   ; account_top                                   ;
; Family                  ; Cyclone                                       ;
; Device                  ; EP1C12Q240C8                                  ;
; Timing Models           ; Final                                         ;
; Met timing requirements ; Yes                                           ;
; Total logic elements    ; 255 / 12,060 ( 2 % )                          ;
; Total pins              ; 30 / 173 ( 17 % )                             ;
; Total virtual pins      ; 0                                             ;
; Total memory bits       ; 0 / 239,616 ( 0 % )                           ;
; Total PLLs              ; 0 / 2 ( 0 % )                                 ;
+-------------------------+-----------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 03/13/2006 22:37:32 ;
; Main task         ; Compilation         ;
; Revision Name     ; phone               ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:15     ;
; Fitter               ; 00:00:16     ;
; Assembler            ; 00:00:05     ;
; Timing Analyzer      ; 00:00:02     ;
; Total                ; 00:00:38     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off phone -c phone
quartus_fit --read_settings_files=off --write_settings_files=off phone -c phone
quartus_asm --read_settings_files=off --write_settings_files=off phone -c phone
quartus_tan --read_settings_files=off --write_settings_files=off phone -c phone --timing_analysis_only