phone.fit.qmsg

卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 13 22:37:47 2006 " "Info: Processing started: Mon Mar 13 22:37:47 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off phone -c phone " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off phone -c phone" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "phone EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"phone\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 28 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 28" {  } { { "account_top.bdf" "" { Schematic "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account_top.bdf" { { 544 336 504 560 "clk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkdiv:33\|clkout Global clock " "Info: Automatically promoted signal \"clkdiv:33\|clkout\" to use Global clock" {  } { { "clkdiv.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/clkdiv.v" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "dismoneyhigh\[0\] " "Warning: Node \"dismoneyhigh\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dismoneyhigh\[0\]" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "dismoneyhigh\[1\] " "Warning: Node \"dismoneyhigh\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dismoneyhigh\[1\]" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "dismoneyhigh\[2\] " "Warning: Node \"dismoneyhigh\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dismoneyhigh\[2\]" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "dismoneyhigh\[3\] " "Warning: Node \"dismoneyhigh\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dismoneyhigh\[3\]" } } } }  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.229 ns register register " "Info: Estimated most critical path is register to register delay of 5.229 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns account2:inst2\|currentState 1 REG LAB_X2_Y22 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y22; Fanout = 23; REG Node = 'account2:inst2\|currentState'" {  } { { "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone_cmp.qrpt" "" { Report "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone_cmp.qrpt" Compiler "phone" "UNKNOWN" "V1" "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone.quartus_db" { Floorplan "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/" "" "" { account2:inst2|currentState } "NODE_NAME" } "" } } { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.442 ns) 0.964 ns account2:inst2\|always5~24 2 COMB LAB_X3_Y22 11 " "Info: 2: + IC(0.522 ns) + CELL(0.442 ns) = 0.964 ns; Loc. = LAB_X3_Y22; Fanout = 11; COMB Node = 'account2:inst2\|always5~24'" {  } { { "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone_cmp.qrpt" "" { Report "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone_cmp.qrpt" Compiler "phone" "UNKNOWN" "V1" "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone.quartus_db" { Floorplan "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/" "" "0.964 ns" { account2:inst2|currentState account2:inst2|always5~24 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.442 ns) 2.330 ns account2:inst2\|warn~222 3 COMB LAB_X3_Y23 8 " "Info: 3: + IC(0.924 ns) + CELL(0.442 ns) = 2.330 ns; Loc. = LAB_X3_Y23; Fanout = 8; COMB Node = 'account2:inst2\|warn~222'" {  } { { "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone_cmp.qrpt" "" { Report "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone_cmp.qrpt" Compiler "phone" "UNKNOWN" "V1" "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone.quartus_db" { Floorplan "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/" "" "1.366 ns" { account2:inst2|always5~24 account2:inst2|warn~222 } "NODE_NAME" } "" } } { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.590 ns) 3.696 ns account2:inst2\|warn~223 4 COMB LAB_X4_Y24 1 " "Info: 4: + IC(0.776 ns) + CELL(0.590 ns) = 3.696 ns; Loc. = LAB_X4_Y24; Fanout = 1; COMB Node = 'account2:inst2\|warn~223'" {  } { { "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone_cmp.qrpt" "" { Report "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone_cmp.qrpt" Compiler "phone" "UNKNOWN" "V1" "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone.quartus_db" { Floorplan "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/" "" "1.366 ns" { account2:inst2|warn~222 account2:inst2|warn~223 } "NODE_NAME" } "" } } { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.795 ns) + CELL(0.738 ns) 5.229 ns account2:inst2\|warn 5 REG LAB_X4_Y22 6 " "Info: 5: + IC(0.795 ns) + CELL(0.738 ns) = 5.229 ns; Loc. = LAB_X4_Y22; Fanout = 6; REG Node = 'account2:inst2\|warn'" {  } { { "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone_cmp.qrpt" "" { Report "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone_cmp.qrpt" Compiler "phone" "UNKNOWN" "V1" "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone.quartus_db" { Floorplan "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/" "" "1.533 ns" { account2:inst2|warn~223 account2:inst2|warn } "NODE_NAME" } "" } } { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.212 ns 42.30 % " "Info: Total cell delay = 2.212 ns ( 42.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.017 ns 57.70 % " "Info: Total interconnect delay = 3.017 ns ( 57.70 % )" {  } {  } 0}  } { { "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone_cmp.qrpt" "" { Report "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone_cmp.qrpt" Compiler "phone" "UNKNOWN" "V1" "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/db/phone.quartus_db" { Floorplan "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/" "" "5.229 ns" { account2:inst2|currentState account2:inst2|always5~24 account2:inst2|warn~222 account2:inst2|warn~223 account2:inst2|warn } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 3 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 3%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 13 22:38:02 2006 " "Info: Processing ended: Mon Mar 13 22:38:02 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Info: Elapsed time: 00:00:16" {  } {  } 0}  } {  } 0}