phone.sim.qmsg

卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 13 21:33:44 2006 " "Info: Processing started: Mon Mar 13 21:33:44 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off phone -c phone " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off phone -c phone" {  } {  } 0}
{ "Info" "ISIM_OVERWRITE_WAVEFORM_INPUTS_WITH_SIMULATION_OUTPUTS" "" "Info: Overwriting simulation input file with simulation results" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|account2\|money\[0\] 10.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 10.0 ns on register \"\|account2\|money\[0\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|account2\|decide0 85.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 85.0 ns on register \"\|account2\|decide0\"" {  } {  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     19.01 % " "Info: Simulation coverage is      19.01 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "6233 " "Info: Number of transitions in simulation is 6233" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 2 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 13 21:33:46 2006 " "Info: Processing ended: Mon Mar 13 21:33:46 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}