phone.map.qmsg

卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(183) " "Warning: Verilog HDL assignment warning at account2.v(183): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 183 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(188) " "Warning: Verilog HDL assignment warning at account2.v(188): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 188 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(210) " "Warning: Verilog HDL assignment warning at account2.v(210): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 210 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(223) " "Warning: Verilog HDL assignment warning at account2.v(223): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 223 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(224) " "Warning: Verilog HDL assignment warning at account2.v(224): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 224 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(226) " "Warning: Verilog HDL assignment warning at account2.v(226): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 226 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(230) " "Warning: Verilog HDL assignment warning at account2.v(230): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 230 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(234) " "Warning: Verilog HDL assignment warning at account2.v(234): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 234 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(238) " "Warning: Verilog HDL assignment warning at account2.v(238): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 238 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(240) " "Warning: Verilog HDL assignment warning at account2.v(240): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 240 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(241) " "Warning: Verilog HDL assignment warning at account2.v(241): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 241 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(244) " "Warning: Verilog HDL assignment warning at account2.v(244): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 244 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(255) " "Warning: Verilog HDL assignment warning at account2.v(255): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 255 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(256) " "Warning: Verilog HDL assignment warning at account2.v(256): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 256 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(258) " "Warning: Verilog HDL assignment warning at account2.v(258): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 258 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(262) " "Warning: Verilog HDL assignment warning at account2.v(262): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 262 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(263) " "Warning: Verilog HDL assignment warning at account2.v(263): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 263 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(270) " "Warning: Verilog HDL assignment warning at account2.v(270): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 270 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(272) " "Warning: Verilog HDL assignment warning at account2.v(272): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 272 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(273) " "Warning: Verilog HDL assignment warning at account2.v(273): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 273 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 account2.v(275) " "Warning: Verilog HDL assignment warning at account2.v(275): truncated value with size 32 to match size of target (4)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 275 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(276) " "Warning: Verilog HDL assignment warning at account2.v(276): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 276 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "account2.v(215) " "Warning: (10270) Verilog HDL statement warning at account2.v(215): incomplete Case Statement has no default case item" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 215 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "account2.v(215) " "Info: Verilog HDL Case Statement information at account2.v(215): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 215 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(281) " "Warning: Verilog HDL assignment warning at account2.v(281): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 281 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 account2.v(283) " "Warning: Verilog HDL assignment warning at account2.v(283): truncated value with size 32 to match size of target (8)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 283 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(292) " "Warning: Verilog HDL assignment warning at account2.v(292): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 292 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(294) " "Warning: Verilog HDL assignment warning at account2.v(294): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 294 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkdiv clkdiv:33 " "Info: Elaborating entity \"clkdiv\" for hierarchy \"clkdiv:33\"" {  } { { "account_top.bdf" "33" { Schematic "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account_top.bdf" { { 528 544 680 576 "33" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkdiv.v(14) " "Warning: Verilog HDL assignment warning at clkdiv.v(14): truncated value with size 32 to match size of target (1)" {  } { { "clkdiv.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/clkdiv.v" 14 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clkdiv.v(15) " "Warning: Verilog HDL assignment warning at clkdiv.v(15): truncated value with size 32 to match size of target (23)" {  } { { "clkdiv.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/clkdiv.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkdiv.v(19) " "Warning: Verilog HDL assignment warning at clkdiv.v(19): truncated value with size 32 to match size of target (1)" {  } { { "clkdiv.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/clkdiv.v" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clkdiv.v(20) " "Warning: Verilog HDL assignment warning at clkdiv.v(20): truncated value with size 32 to match size of target (23)" {  } { { "clkdiv.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/clkdiv.v" 20 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "p7segment_new p7segment_new:inst4 " "Info: Elaborating entity \"p7segment_new\" for hierarchy \"p7segment_new:inst4\"" {  } { { "account_top.bdf" "inst4" { Schematic "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account_top.bdf" { { 672 1184 1336 768 "inst4" "" } } } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "287 " "Info: Implemented 287 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "23 " "Info: Implemented 23 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "257 " "Info: Implemented 257 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 55 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 55 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 13 22:37:45 2006 " "Info: Processing ended: Mon Mar 13 22:37:45 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Info: Elapsed time: 00:00:15" {  } {  } 0}  } {  } 0}