clkdiv.v.bak

卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能

//输入20MHz，输出4Hz
module clkdiv(clk,clkout);
  parameter clk_count_max=5000000-1 //2^23=8388608
  input clk;
  output clkout;
  reg clkout;
  reg[22:0] clk_count;
  
  always @(clk)
    begin
      if(clk_count>=clk_count_max)
        begin
          clkout<=1;
          clk_count<=0;
        end
      else
        begin
          clkout<=0;
          clk_count<=clk_count+1;
        end
   end
endmodule